公开(公告)号：US20190252540A1

公开(公告)日：2019-08-15

申请号：US16394671

申请日：2019-04-25

申请人： Samsung Electronics Co., Ltd.

发明人： Sung-Min Kim ,  Kyung-Seok Oh ,  Cheol Kim ,  Heon-Jong Shin ,  Jong-Ryeol Yoo ,  Hyun-Jung Lee ,  Seong-Hoon Jeong

IPC分类号： H01L29/78 ,  H01L27/12 ,  H01L29/423 ,  H01L21/84 ,  H01L29/66

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/42392 ,  H01L29/66795

摘要： Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a lower fin that protrudes from a substrate and extends in a first direction, an oxide film the lower fin, an upper fin that protrudes from the oxide film and that is spaced apart from the lower fin at a position corresponding to the lower fin, and a gate structure the upper fin that extends in a second direction to intersect the upper fin, wherein germanium (Ge) is included in a portion of the oxide film located between the lower fin and the upper fin.

公开(公告)号：US09202844B2

公开(公告)日：2015-12-01

申请号：US13966423

申请日：2013-08-14

申请人： Samsung Electronics Co., Ltd.

发明人： Jae-Jong Han ,  Yoon-Goo Kang ,  Won-Seok Yoo ,  Kong-Soo Lee ,  Han-Jin Lim ,  Seong-Hoon Jeong

IPC分类号： H01L27/24 ,  H01L45/00

CPC分类号： H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144

摘要： A semiconductor device includes a lower interconnection having second conductivity-type impurities on a substrate having first conductivity-type impurities. A switching device is on the lower interconnection. A first blocking layer is provided between the lower interconnection and the switching device. The first blocking layer includes carbon (C), germanium (Ge), or a combination thereof. A second blocking layer may be provided between the substrate and the lower interconnection.

摘要翻译： 半导体器件包括在具有第一导电型杂质的衬底上的具有第二导电类型杂质的下互连。 开关装置在较低的互连上。 第一阻挡层设置在下互连和开关器件之间。 第一阻挡层包括碳（C），锗（Ge）或其组合。 第二阻挡层可以设置在基板和下部互连件之间。

公开(公告)号：US10319858B2

公开(公告)日：2019-06-11

申请号：US16128152

申请日：2018-09-11

申请人： Samsung Electronics Co., Ltd.

发明人： Sung-Min Kim ,  Kyung-Seok Oh ,  Cheol Kim ,  Heon-Jong Shin ,  Jong-Ryeol Yoo ,  Hyun-Jung Lee ,  Seong-Hoon Jeong

IPC分类号： H01L21/84 ,  H01L27/12 ,  H01L29/66 ,  H01L29/78

摘要： Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a lower fin that protrudes from a substrate and extends in a first direction, an oxide film the lower fin, an upper fin that protrudes from the oxide film and that is spaced apart from the lower fin at a position corresponding to the lower fin, and a gate structure the upper fin that extends in a second direction to intersect the upper fin, wherein germanium (Ge) is included in a portion of the oxide film located between the lower fin and the upper fin.

公开(公告)号：US09916414B2

公开(公告)日：2018-03-13

申请号：US14920548

申请日：2015-10-22

申请人： Samsung Electronics Co., Ltd.

发明人： Seong-Hoon Jeong ,  Moo-Kyoung Chung ,  Young-Chul Cho ,  Hee-Jun Shim ,  Jin-Sae Jung ,  Yen-Jo Han

IPC分类号： G06F17/50 ,  G06F11/36

CPC分类号： G06F17/5081 ,  G06F11/3684 ,  G06F17/5009

摘要： An apparatus for generating a test case includes a constrained description generator configured to define a plurality of constrained verification spaces in a total verification space, and generate a constrained description for each of the plurality of constrained verification spaces; and a test case generator configured to generate a test case using the constrained description.

公开(公告)号：US20160042116A1

公开(公告)日：2016-02-11

申请号：US14920548

申请日：2015-10-22

申请人： Samsung Electronics Co., Ltd.

发明人： Seong-Hoon Jeong ,  Moo-Kyoung Chung ,  Young-Chul Cho ,  Hee-Jun Shim ,  Jin-Sae Jung ,  Yen-Jo Han

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F11/3684 ,  G06F17/5009

摘要： An apparatus for generating a test case includes a constrained description generator configured to define a plurality of constrained verification spaces in a total verification space, and generate a constrained description for each of the plurality of constrained verification spaces; and a test case generator configured to generate a test case using the constrained description.

摘要翻译： 用于生成测试用例的装置包括：受限描述发生器，其被配置为在总验证空间中定义多个约束验证空间，并且为所述多个约束验证空间中的每一个生成约束描述; 以及被配置为使用约束描述生成测试用例的测试用例生成器。

公开(公告)号：US20140158964A1

公开(公告)日：2014-06-12

申请号：US13966423

申请日：2013-08-14

申请人： Samsung Electronics Co., Ltd.

发明人： Jae-Jong HAN ,  Yoon-Goo Kang ,  Won-Seok Yoo ,  Kong-Soo Lee ,  Han-Jin Lim ,  Seong-Hoon Jeong

IPC分类号： H01L45/00

CPC分类号： H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144

摘要： A semiconductor device includes a lower interconnection having second conductivity-type impurities on a substrate having first conductivity-type impurities. A switching device is on the lower interconnection. A first blocking layer is provided between the lower interconnection and the switching device. The first blocking layer includes carbon (C), germanium (Ge), or a combination thereof. A second blocking layer may be provided between the substrate and the lower interconnection.

摘要翻译： 半导体器件包括在具有第一导电型杂质的衬底上的具有第二导电类型杂质的下互连。 开关装置在较低的互连上。 第一阻挡层设置在下互连和开关器件之间。 第一阻挡层包括碳（C），锗（Ge）或其组合。 第二阻挡层可以设置在基板和下部互连件之间。

公开(公告)号：US10379983B2

公开(公告)日：2019-08-13

申请号：US14980903

申请日：2015-12-28

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Young-Chul Cho ,  Seong-Hoon Jeong ,  Jin-Sae Jung

IPC分类号： G06F9/44 ,  G06F13/10 ,  G06F13/12 ,  G06F11/26 ,  G06F11/263 ,  G06F17/50

摘要： A simulation apparatus and a distribution simulation system are disclosed. The simulation apparatus, according to one example, includes a simulation executer configured to execute a simulation task, a data storage configured to store data related to the simulation task based on a data storage policy that is set in advance of the execution of the simulation tasks, and a data updater configured to update the data stored in the data storage to most recent data by comparing the data stored in the data storage with data stored in another simulation apparatus.

公开(公告)号：US08987694B2

公开(公告)日：2015-03-24

申请号：US13729742

申请日：2012-12-28

申请人： Samsung Electronics Co., Ltd.

发明人： Jae-Jong Han ,  Kong-Soo Lee ,  Yoon-Goo Kang ,  Ho-Kyun An ,  Seong-Hoon Jeong

IPC分类号： H01L29/02 ,  H01L45/00 ,  H01L27/102 ,  H01L27/24 ,  H01L27/10

CPC分类号： H01L45/04 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/124 ,  H01L45/141 ,  H01L45/143 ,  H01L45/144

摘要： Semiconductor devices, and methods of manufacturing the same, include a field region in a semiconductor substrate to define an active region. An interlayer insulating layer is on the semiconductor substrate. A semiconductor pattern is within a hole vertically extending through the interlayer insulating layer. The semiconductor pattern is in contact with the active region. A barrier region is between the semiconductor pattern and the interlayer insulating layer. The barrier region includes a first buffer dielectric material and a barrier dielectric material. The first buffer dielectric material is between the barrier dielectric material and the semiconductor pattern, and the barrier dielectric material is spaced apart from both the semiconductor pattern and the active region.

摘要翻译： 半导体器件及其制造方法包括半导体衬底中的场区以限定有源区。 层间绝缘层位于半导体衬底上。 半导体图案在垂直延伸穿过层间绝缘层的孔内。 半导体图案与有源区域接触。 阻挡区域在半导体图案和层间绝缘层之间。 阻挡区域包括第一缓冲介电材料和阻挡介电材料。 第一缓冲电介质材料在阻挡介电材料和半导体图案之间，并且阻挡介电材料与半导体图案和有源区两者间隔开。