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    Vertical memory devices and methods of manufacturing the same
    2.
    发明授权
    Vertical memory devices and methods of manufacturing the same 有权

    公开(公告)号：US10403638B2

    公开(公告)日：2019-09-03

    申请号：US15610923

    申请日：2017-06-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Joon-Suk Lee ,  Hong-Suk Kim ,  Jae-Young Ahn ,  Han-Jin Lim

    IPC: H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L27/1157 ,  H01L27/11582

    Abstract: A vertical memory device includes a first structure having a lower semiconductor pattern structure filling a recess on a substrate and protruding from an upper surface of the substrate in a first direction substantially perpendicular to the upper surface of the substrate, the lower semiconductor pattern structure including a first undoped semiconductor pattern, a doped semiconductor pattern, and a second undoped semiconductor pattern sequentially stacked, and a lower surface of the doped semiconductor pattern being lower than the upper surface of the substrate, and an upper semiconductor pattern extending in the first direction on the lower semiconductor pattern structure, and a plurality of gate electrodes surrounding a sidewall of the first structure, the plurality of gate electrodes being at a plurality of levels, respectively, so as to be spaced apart from each other in the first direction.

    Semiconductor devices
    4.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US10403641B2

    公开(公告)日：2019-09-03

    申请号：US15987545

    申请日：2018-05-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sung-Gil Kim ,  Seul-Ye Kim ,  Hong-suk Kim ,  Phil-Ouk Nam ,  Jae-Young Ahn ,  Ji-Hoon Choi

    IPC: H01L29/792 ,  H01L27/11582 ,  H01L27/11556 ,  H01L21/768 ,  H01L21/311

    Abstract: A semiconductor device may include a plurality of conductive patterns and an insulation pattern. The plurality of conductive patterns may be formed on a substrate. The plurality of conductive patterns may be spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate. Each of the plurality of conductive patterns may have an extension portion and a step portion. The step portion may be disposed at an edge of the corresponding conductive pattern. The insulation pattern may be formed between the plurality of conductive patterns in the vertical direction. A lower surface and an upper surface of the step portion of each of the plurality of conductive patterns may be bent upwardly.

    Three-dimensional semiconductor memory devices and methods of fabricating the same
    6.
    发明授权
    Three-dimensional semiconductor memory devices and methods of fabricating the same 有权
    三维半导体存储器件及其制造方法

    公开(公告)号：US08872256B2

    公开(公告)日：2014-10-28

    申请号：US13796118

    申请日：2013-03-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Juyul Lee ,  Bumsu Kim ,  Kwangmin Park ,  Hyun Park ,  Jae-Young Ahn ,  Dongchul Yoo ,  Jongsik Chun ,  Kihyun Hwang

    IPC: H01L27/105

    CPC classification number: H01L27/11582 ,  H01L27/1052 ,  H01L29/7926

    Abstract: A three-dimensional (3D) semiconductor memory device includes an electrode separation pattern, a stack structure, a data storage layer, and a channel structure. The electrode separation pattern is disposed on a substrate. A stack structure is disposed on a sidewall of the electrode separation pattern. The stack structure includes a corrugated sidewall opposite to the sidewall of the electrode separation pattern. The sidewall of the electrode separation pattern is vertical to the substrate. A data storage layer is disposed on the corrugated sidewall. A channel structure is disposed on the charge storage layer.

    Abstract translation: 三维（3D）半导体存储器件包括电极分离图案，堆叠结构，数据存储层和沟道结构。 电极分离图案设置在基板上。 堆叠结构设置在电极分离图案的侧壁上。 堆叠结构包括与电极分离图案的侧壁相对的波纹状侧壁。 电极分离图案的侧壁垂直于基板。 数据存储层设置在波纹侧壁上。 通道结构设置在电荷存储层上。

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