公开(公告)号：US09653565B2

公开(公告)日：2017-05-16

申请号：US14865078

申请日：2015-09-25

Applicant: Samsung Electronics Co., Ltd

Inventor： Byong-hyun Jang ,  Dongchul Yoo ,  Jaeyoung Ahn ,  Hunhyeong Lim

IPC: H01L29/49 ,  H01L27/11582

CPC classification number: H01L29/495 ,  H01L27/11582

Abstract: A three dimensional semiconductor memory device includes a vertical channel structure extending in a vertical direction on a substrate; interlayer insulating layers surrounding the vertical channel structure and being stacked in the vertical direction on the substrate, gate electrodes surrounding the vertical channel structure and being disposed between the interlayer insulating layers, corners of the gate electrodes adjacent to the vertical channel structure being rounded, and auxiliary gate insulating patterns disposed between the gate electrodes and the vertical channel structure, wherein a side surface of the auxiliary gate insulating pattern is substantially coplanar with a side surface of the interlayer insulating layer in the vertical direction on the substrate.

公开(公告)号：US10103170B2

公开(公告)日：2018-10-16

申请号：US15784635

申请日：2017-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byong-hyun Jang ,  Dongchul Yoo ,  Woojin Jang ,  Jaeyoung Ahn ,  Junkyu Yang

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L23/528 ,  H01L29/51 ,  H01L27/11568 ,  H01L21/311 ,  H01L21/28 ,  H01L29/10 ,  H01L29/06 ,  H01L21/762 ,  H01L27/11565

Abstract: A semiconductor device includes word lines vertically stacked on top of each other on a substrate, insulating patterns between the word lines, a vertical pillar connected to the substrate, and residual sacrificial patterns on the substrate at sides of the word lines. The vertical pillar penetrates the word lines and the insulating patterns. Each of the insulating patterns includes a first portion between the word lines and a second portion extending from the first portion and between the residual sacrificial patterns. A first thickness of the first portion is smaller than a second thickness of the second portion.

公开(公告)号：US10658375B2

公开(公告)日：2020-05-19

申请号：US15975861

申请日：2018-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gukhyon Yon ,  Dongwoo Kim ,  Kihyun Hwang ,  Dongkyum Kim ,  Dongchul Yoo

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/24 ,  H01L27/11578 ,  H01L27/11556 ,  H01L27/11575 ,  H01L45/00

Abstract: A three-dimensional semiconductor memory device includes a peripheral circuit structure on a substrate, a horizontal active layer on the peripheral circuit structure, stacks provided on the horizontal active layer to include a plurality of electrodes, a vertical structure vertically penetrating the stacks, a common source region between ones of the stacks and in the horizontal active layer, and pick-up regions in the horizontal active layer. The horizontal active layer includes first, second, and third active semiconductor layers sequentially stacked on the peripheral circuit structure. The first and third active semiconductor layers are doped to have high and low impurity concentrations, respectively, and the second active semiconductor layer includes an impurity diffusion restraining material.

公开(公告)号：US09559111B2

公开(公告)日：2017-01-31

申请号：US14790969

申请日：2015-07-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongchul Yoo ,  Phil Ouk Nam ,  Junkyu Yang ,  Woong Lee ,  Woosung Lee ,  JinGyun Kim ,  Daehong Eom

IPC: H01L29/792 ,  H01L27/115 ,  H01L29/423

CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L29/04 ,  H01L29/1037 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/7926

Abstract: A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate; horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively; vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars, respectively; and epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures, wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures.

Abstract translation: 一种三维（3D）半导体存储器件及其制造方法，该器件包括堆叠在衬底上的绝缘层; 绝缘层之间的水平结构，分别包括栅电极的水平结构; 垂直结构分别穿透绝缘层和水平结构，垂直结构分别包括半导体柱; 和外延图案，每个外延图案在衬底和每个垂直结构之间，其中外延图案的最小宽度小于垂直结构中对应的一个的宽度。

公开(公告)号：US20150041882A1

公开(公告)日：2015-02-12

申请号：US14493849

申请日：2014-09-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juyul Lee ,  Bumsu Kim ,  Kwangmin Park ,  Hyun Park ,  Jae-young Ahn ,  Dongchul Yoo ,  Jongsik Chun ,  Kihyun Hwang

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/1052 ,  H01L29/7926

Abstract: A three-dimensional (3D) semiconductor memory device includes an electrode separation pattern, a stack structure, a data storage layer, and a channel structure. The electrode separation pattern is disposed on a substrate. A stack structure is disposed on a sidewall of the electrode separation pattern. The stack structure includes a corrugated sidewall opposite to the sidewall of the electrode separation pattern. The sidewall of the electrode separation pattern is vertical to the substrate. A data storage layer is disposed on the corrugated sidewall. A channel structure is disposed on the charge storage layer.

Abstract translation: 三维（3D）半导体存储器件包括电极分离图案，堆叠结构，数据存储层和沟道结构。 电极分离图案设置在基板上。 堆叠结构设置在电极分离图案的侧壁上。 堆叠结构包括与电极分离图案的侧壁相对的波纹状侧壁。 电极分离图案的侧壁垂直于基板。 数据存储层设置在波纹侧壁上。 通道结构设置在电荷存储层上。

公开(公告)号：US09899411B2

公开(公告)日：2018-02-20

申请号：US15414345

申请日：2017-01-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongchul Yoo ,  Phil Ouk Nam ,  Junkyu Yang ,  Woong Lee ,  Woosung Lee ,  JinGyun Kim ,  Daehong Eom

IPC: H01L21/8247 ,  H01L27/11582 ,  H01L27/1157 ,  H01L29/423 ,  H01L29/10 ,  H01L29/04 ,  H01L29/51

CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L29/04 ,  H01L29/1037 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/7926

Abstract: A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate; horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively; vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars, respectively; and epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures, wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures.

公开(公告)号：US08872256B2

公开(公告)日：2014-10-28

申请号：US13796118

申请日：2013-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyul Lee ,  Bumsu Kim ,  Kwangmin Park ,  Hyun Park ,  Jae-Young Ahn ,  Dongchul Yoo ,  Jongsik Chun ,  Kihyun Hwang

IPC: H01L27/105

CPC classification number: H01L27/11582 ,  H01L27/1052 ,  H01L29/7926

Abstract: A three-dimensional (3D) semiconductor memory device includes an electrode separation pattern, a stack structure, a data storage layer, and a channel structure. The electrode separation pattern is disposed on a substrate. A stack structure is disposed on a sidewall of the electrode separation pattern. The stack structure includes a corrugated sidewall opposite to the sidewall of the electrode separation pattern. The sidewall of the electrode separation pattern is vertical to the substrate. A data storage layer is disposed on the corrugated sidewall. A channel structure is disposed on the charge storage layer.

Abstract translation: 三维（3D）半导体存储器件包括电极分离图案，堆叠结构，数据存储层和沟道结构。 电极分离图案设置在基板上。 堆叠结构设置在电极分离图案的侧壁上。 堆叠结构包括与电极分离图案的侧壁相对的波纹状侧壁。 电极分离图案的侧壁垂直于基板。 数据存储层设置在波纹侧壁上。 通道结构设置在电荷存储层上。

公开(公告)号：US09202819B2

公开(公告)日：2015-12-01

申请号：US14493849

申请日：2014-09-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juyul Lee ,  Bumsu Kim ,  Kwangmin Park ,  Hyun Park ,  Jae-young Ahn ,  Dongchul Yoo ,  Jongsik Chun ,  Kihyun Hwang

IPC: H01L27/105 ,  H01L27/115 ,  H01L29/792

CPC classification number: H01L27/11582 ,  H01L27/1052 ,  H01L29/7926

Abstract: A three-dimensional (3D) semiconductor memory device includes an electrode separation pattern, a stack structure, a data storage layer, and a channel structure. The electrode separation pattern is disposed on a substrate. A stack structure is disposed on a sidewall of the electrode separation pattern. The stack structure includes a corrugated sidewall opposite to the sidewall of the electrode separation pattern. The sidewall of the electrode separation pattern is vertical to the substrate. A data storage layer is disposed on the corrugated sidewall. A channel structure is disposed on the charge storage layer.

Abstract translation: 三维（3D）半导体存储器件包括电极分离图案，堆叠结构，数据存储层和沟道结构。 电极分离图案设置在基板上。 堆叠结构设置在电极分离图案的侧壁上。 堆叠结构包括与电极分离图案的侧壁相对的波纹状侧壁。 电极分离图案的侧壁垂直于基板。 数据存储层设置在波纹侧壁上。 通道结构设置在电荷存储层上。

公开(公告)号：US09184302B2

公开(公告)日：2015-11-10

申请号：US13765213

申请日：2013-02-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanjin Park ,  Kihyun Hwang ,  Dongchul Yoo ,  Junkyu Yang ,  Gyungjin Min ,  Yoochul Kong ,  Hanmei Choi

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L29/788 ,  H01L27/115 ,  H01L29/66 ,  H01L29/792 ,  H01L23/538

CPC classification number: H01L29/788 ,  H01L23/5384 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a three dimensional semiconductor device. The device may include mold layers vertically and sequentially stacked, a conductive pattern between the stacked mold layers, a plugging pattern vertically penetrating the stacked mold layers, an intermediate pattern between the conductive pattern and the plugging pattern, and protective layer patterns between the mold layers and the plugging pattern, wherein the protective layer patterns are separated by the intermediate pattern.

Abstract translation: 提供三维半导体器件。 该装置可以包括垂直和顺序堆叠的模具层，堆叠的模具层之间的导电图案，垂直穿过堆叠的模具层的插入图案，导电图案和插入图案之间的中间图案，以及模具层之间的保护层图案 和封堵图案，其中保护层图案由中间图案分离。

公开(公告)号：US09076879B2

公开(公告)日：2015-07-07

申请号：US13974122

申请日：2013-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongchul Yoo ,  Phil Ouk Nam ,  Junkyu Yang ,  Woong Lee ,  Woosung Lee ,  JinGyun Kim ,  Daehong Eom

IPC: H01L29/792 ,  H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L29/04 ,  H01L29/1037 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/7926

Abstract: A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate; horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively; vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars, respectively; and epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures, wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures.

Abstract translation: 一种三维（3D）半导体存储器件及其制造方法，该器件包括堆叠在衬底上的绝缘层; 绝缘层之间的水平结构，分别包括栅电极的水平结构; 垂直结构分别穿透绝缘层和水平结构，垂直结构分别包括半导体柱; 和外延图案，每个外延图案在衬底和每个垂直结构之间，其中外延图案的最小宽度小于垂直结构中对应的一个的宽度。