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    Semiconductor devices
    1.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US11417603B2

    公开(公告)日：2022-08-16

    申请号：US16933133

    申请日：2020-07-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaegoo Lee

    IPC: H01L23/535 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11582

    Abstract: A semiconductor device a substrate; conductive patterns on the substrate, the conductive patterns being spaced apart from each other in a vertical direction perpendicular to a surface of the substrate, and an edge of the conductive patterns including a step portion such that an end of one conductive pattern is not overlapped in the vertical direction with conductive patterns positioned thereover; insulation patterns between the conductive patterns; sidewall insulation patterns on the sidewalls of the conductive patterns to cover sidewalls of the conductive patterns; upper pad patterns on upper surfaces of the step portion of the conductive patterns and upper surfaces of a portion of the sidewall insulation patterns; an insulating interlayer covering the conductive patterns, the insulation patterns, the sidewall insulation patterns, and the upper pad patterns; and contact plugs passing through the insulating interlayer, the contact plugs contacting the upper pad patterns, respectively.

    Methods of forming semiconductor memory devices
    2.
    发明授权
    Methods of forming semiconductor memory devices 有权
    形成半导体存储器件的方法

    公开(公告)号：US09305933B2

    公开(公告)日：2016-04-05

    申请号：US14516996

    申请日：2014-10-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaegoo Lee

    IPC: H01L29/792 ,  H01L27/115 ,  G11C16/04

    CPC classification number: H01L27/11563 ,  G11C16/0408 ,  G11C16/0483 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

    Abstract: Methods of fabricating a semiconductor device are provided. The method includes alternately stacking first material layers and second material layers on a substrate to form a stacked structure, forming a through hole penetrating the stacked structure, forming a data storage layer on a sidewall of the through hole, forming a semiconductor pattern electrically connected to the substrate on an inner sidewall of the data storage layer, etching an upper portion of the data storage layer to form a first recessed region exposing an outer sidewall of the semiconductor pattern, and forming a first conductive layer in the first recessed region. Related devices are also disclosed.

    Abstract translation: 提供制造半导体器件的方法。 该方法包括在基板上交替堆叠第一材料层和第二材料层以形成层叠结构，形成穿透层叠结构的通孔，在通孔的侧壁上形成数据存储层，形成电连接到 在数据存储层的内侧壁上的衬底，蚀刻数据存储层的上部以形成暴露半导体图案的外侧壁的第一凹部，以及在第一凹陷区域中形成第一导电层。 还公开了相关设备。

    THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME
    3.
    发明申请
    THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME 审中-公开
    三维半导体存储器件及其制造方法

    公开(公告)号：US20150303215A1

    公开(公告)日：2015-10-22

    申请号：US14753713

    申请日：2015-06-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： SUNG-IL CHANG ,  Youngwoo Park ,  Jaegoo Lee

    IPC: H01L27/115 ,  H01L29/423

    CPC classification number: H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/42324 ,  H01L29/4234

    Abstract: A 3D semiconductor device includes an electrode structure has electrodes stacked on a substrate, semiconductor patterns penetrating the electrode structure, charge storing patterns interposed between the semiconductor patterns and the electrode structure, and blocking insulating patterns interposed between the charge storing patterns and the electrode structure. Each of the blocking insulating patterns surrounds the semiconductor patterns, and the charge storing patterns are horizontally spaced from each other and configured in such a way as to each be disposed around a respective one of the semiconductor patterns. Also, each of the charge storing patterns includes a plurality of horizontal segments, each interposed between vertically adjacent ones of the electrodes.

    Abstract translation: 一种3D半导体器件包括：电极结构，其具有堆叠在基板上的电极，穿透电极结构的半导体图案，插入在半导体图案和电极结构之间的电荷存储图案，以及插入在电荷存储图案和电极结构之间的绝缘图案。 每个隔离绝缘图案包围半导体图案，并且电荷存储图案彼此水平间隔并且以这样的方式配置，以使得每个隔离绝缘图案围绕相应的一个半导体图案设置。 而且，每个电荷存储图案包括多个水平段，每个水平段插入垂直相邻的电极之间。

    Three-dimensional memory device including word line including polysilicon and metal
    4.
    发明授权
    Three-dimensional memory device including word line including polysilicon and metal 有权

    公开(公告)号：US11430807B2

    公开(公告)日：2022-08-30

    申请号：US16885597

    申请日：2020-05-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaegoo Lee

    IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11519 ,  G11C7/18 ,  H01L27/11556 ,  H01L23/522 ,  G11C8/14 ,  H01L27/11526

    Abstract: A 3D memory device and a method of manufacturing the same, the device including a substrate including a cell and an extension region; a cell stack including insulation layers and word lines alternately stacked on the substrate; channel structures vertically passing through the cell stack; a word line separation layer vertically passing through the cell stack and extending lengthwise in a first direction; a contact plug vertically connected to the word lines on the extension region; and a bit line extending lengthwise in a second direction on the channel structures, wherein each of the word lines includes an inner pattern including polysilicon; and an outer pattern including metal, the outer pattern surrounds an outer surface of the inner pattern, the channel structures vertically pass through the inner pattern, and the contact plug is on the outer pattern.

    SEMICONDUCTOR DEVICES
    5.
    发明申请
    SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20210193812A1

    公开(公告)日：2021-06-24

    申请号：US16998342

    申请日：2020-08-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaegoo Lee

    IPC: H01L29/423 ,  H01L27/11582 ,  H01L27/11556

    Abstract: A semiconductor device includes a substrate having a first region and a second region, gate electrodes stacked in the first region and forming a pad region having a stepped shape extending by different lengths in the second region, interlayer insulating layers alternately stacked with the gate electrodes, channel structures passing through the gate electrodes in the first region and including a channel layer, separation regions passing through the gate electrodes in the first and second regions, an etch-stop layer disposed on uppermost gate electrodes, among the gate electrodes forming the pad region in the second region, not to overlap the first region and the separation regions, a cell region insulating layer covering the gate electrodes and the etch-stop layer, and contact plugs passing through the cell region insulating layer and the etch-stop layer in the second region and connected to the gate electrodes in the pad region.

    Semiconductor device and method of fabricating the same
    7.
    发明授权
    Semiconductor device and method of fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号：US09472568B2

    公开(公告)日：2016-10-18

    申请号：US14502115

    申请日：2014-09-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yoocheol Shin ,  Jaegoo Lee ,  Young-Jin Kwon ,  Jintaek Park

    IPC: H01L27/115 ,  H01L21/768

    CPC classification number: H01L27/11582 ,  H01L21/76802 ,  H01L27/1157 ,  H01L27/11575

    Abstract: A semiconductor device is provided as follows. A peripheral circuit structure is disposed on a first substrate. A cell array structure is disposed on the peripheral circuit structure. A second substrate is interposed between the peripheral circuit structure and the cell array structure. The cell array structure includes a stacked structure, a through hole and a vertical semiconductor pattern. The stacked structure includes gate electrodes stacked on the second substrate. The through hole penetrates the stacked structure and the second substrate to expose the peripheral circuit structure. The vertical semiconductor pattern is disposed on the peripheral circuit structure, filling the through hole.

    Abstract translation: 如下提供半导体器件。 外围电路结构设置在第一基板上。 电池阵列结构设置在外围电路结构上。 第二基板介于外围电路结构和电池阵列结构之间。 电池阵列结构包括堆叠结构，通孔和垂直半导体图案。 层叠结构包括层叠在第二基板上的栅电极。 通孔贯穿堆叠结构和第二基板，露出外围电路结构。 垂直半导体图案设置在外围电路结构上，填充通孔。

    Semiconductor device and method of manufacturing the semiconductor device
    8.
    发明授权
    Semiconductor device and method of manufacturing the semiconductor device 有权

    公开(公告)号：US10229927B2

    公开(公告)日：2019-03-12

    申请号：US14725476

    申请日：2015-05-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dohyun Lee ,  Jaegoo Lee ,  Young-Jin Kwon ,  Youngwoo Park ,  Jaeduk Lee

    IPC: H01L27/115 ,  H01L27/11582 ,  H01L29/10 ,  H01L29/792 ,  H01L27/1157

    Abstract: A semiconductor device includes a lower stack structure including lower gate electrodes and lower insulating layers that are alternately and repeatedly stacked on a substrate. The semiconductor device includes an upper stack structure including upper gate electrodes and upper insulating layers that are alternately and repeatedly stacked on the lower stack structure. A lower channel structure penetrates the lower stack structure. An upper channel structure penetrates and is connected to the upper stack structure. A lower vertical insulator is disposed between the lower stack structure and the lower channel structure. The lower channel structure includes a first vertical semiconductor pattern connected to the substrate, and a first connecting semiconductor pattern disposed on the first vertical semiconductor pattern. The upper channel structure includes a second vertical semiconductor pattern electrically connected to the first vertical semiconductor pattern with the first connecting semiconductor pattern disposed therebetween.

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