公开(公告)号：US11296277B2

公开(公告)日：2022-04-05

申请号：US16589456

申请日：2019-10-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghoon Ahn ,  Oik Kwon ,  Jeonghee Park ,  Kihyun Hwang

IPC: H01L43/08 ,  H01L27/22 ,  H01L27/24 ,  H01L45/00 ,  H01L43/12 ,  H01L43/10

Abstract: A variable resistance memory device is provided including a plurality of lower electrodes disposed on a substrate. A plurality of variable resistors are disposed on the plurality of lower electrodes. A plurality of upper electrodes are disposed on the plurality of variable resistors. An interlayer insulating layer fills a space in the plurality of variable resistors. An anti-oxidation layer is disposed between the plurality of variable resistors and the interlayer insulating layer. The anti-oxidation layer covers side surfaces of the plurality of variable resistors, and the anti-oxidation layer comprises silicon and/or carbon.

公开(公告)号：US10903327B2

公开(公告)日：2021-01-26

申请号：US16859437

申请日：2020-04-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang Soo Seol ,  Chanjin Park ,  Kihyun Hwang ,  Hanmei Choi ,  Sunghoi Hur ,  Wansik Hwang ,  Toshiro Nakanishi ,  Kwangmin Park ,  Juyul Lee

IPC: H01L21/3213 ,  H01L29/423 ,  H01L27/06 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/792 ,  H01L27/11582 ,  H01L29/51

Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

公开(公告)号：US08980731B2

公开(公告)日：2015-03-17

申请号：US13724632

申请日：2012-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Ho Kim ,  Sunghae Lee ,  Hanvit Yang ,  Dongwoo Kim ,  Chaeho Kim ,  Daehyun Jang ,  Ju-Eun Kim ,  Yong-Hoon Son ,  Sangryol Yang ,  Myoungbum Lee ,  Kihyun Hwang

IPC: H01L21/04 ,  H01L21/82 ,  H01L21/336 ,  H01L21/3205 ,  H01L29/76 ,  H01L29/792 ,  H01L27/115 ,  H01L29/66

CPC classification number: H01L21/04 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

Abstract: Methods of forming a semiconductor device are provided. The methods may include forming first and second layers that are alternately and repeatedly stacked on a substrate, and forming an opening penetrating the first and second layers. The methods may also include forming a first semiconductor pattern in the opening. The methods may additionally include forming an insulation pattern on the first semiconductor pattern. The methods may further include forming a second semiconductor pattern on the insulation pattern. The methods may also include providing dopants in the first semiconductor pattern. Moreover, the methods may include thermally treating a portion of the first semiconductor pattern to form a third semiconductor pattern.

Abstract translation: 提供了形成半导体器件的方法。 所述方法可以包括形成在衬底上交替和重复堆叠的第一和第二层，以及形成穿透第一层和第二层的开口。 所述方法还可以包括在开口中形成第一半导体图案。 所述方法还可以包括在第一半导体图案上形成绝缘图案。 所述方法还可以包括在绝缘图案上形成第二半导体图案。 所述方法还可以包括在第一半导体图案中提供掺杂剂。 此外，所述方法可以包括热处理第一半导体图案的一部分以形成第三半导体图案。

公开(公告)号：US08765538B2

公开(公告)日：2014-07-01

申请号：US14061304

申请日：2013-10-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bio Kim ,  Kihyun Hwang ,  Jaeyoung Ahn ,  SeungHyun Lim ,  Dongwoo Kim

IPC: H01L21/336

CPC classification number: H01L29/66666 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

Abstract: Provided are three-dimensional semiconductor memory devices and methods of forming the same. The device includes a substrate, conductive patterns stacked on the substrate, and an active pattern penetrating the conductive patterns to be connected to the substrate. The active pattern may include a first doped region provided in an upper portion of the active pattern, and a diffusion-resistant doped region overlapped with at least a portion of the first doped region. The diffusion-resistant doped region may be a region doped with carbon.

Abstract translation: 提供三维半导体存储器件及其形成方法。 该器件包括衬底，堆叠在衬底上的导电图案，以及穿透要连接到衬底的导电图案的有源图案。 有源图案可以包括设置在有源图案的上部的第一掺杂区域和与第一掺杂区域的至少一部分重叠的扩散阻抗掺杂区域。 扩散阻止掺杂区域可以是掺杂有碳的区域。

公开(公告)号：US12113108B2

公开(公告)日：2024-10-08

申请号：US17472926

申请日：2021-09-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dohee Kim ,  Gyeom Kim ,  Jinbum Kim ,  Haejun Yu ,  Kyungin Choi ,  Kihyun Hwang ,  Seunghun Lee

IPC: H01L29/41 ,  H01L27/088 ,  H01L29/417

CPC classification number: H01L29/41775 ,  H01L27/0886

Abstract: An integrated circuit device includes a plurality of gate structures each including a gate line extending on a fin-type active region and insulation spacers on sidewalls of the gate line; a source/drain contact between first and second gate structures, and having opposing sides that are asymmetric in the first horizontal direction; and an insulation liner on sidewalls of the source/drain contact. The source/drain contact includes a lower contact portion and an upper contact portion having a horizontal extension that extends on an upper corner of the first gate structure, the insulation liner includes a first local region between the upper corner and the horizontal extension and a second local region that is farther from the substrate than the first local region, and a thickness of the first local region is greater than that of the second local region.

公开(公告)号：US11888028B2

公开(公告)日：2024-01-30

申请号：US17862453

申请日：2022-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinbum Kim ,  Dahye Kim ,  Seokhoon Kim ,  Jaemun Kim ,  Ilgyou Shin ,  Haejun Yu ,  Kyungin Choi ,  Kihyun Hwang ,  Sangmoon Lee ,  Seung Hun Lee ,  Keun Hwi Cho

IPC: H01L29/08 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L29/161 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L29/0847 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/78696

Abstract: A semiconductor device includes an active pattern on a substrate, a pair of source/drain patterns on the active pattern, a channel pattern between the pair of source/drain patterns, the channel pattern including semiconductor patterns stacked to be spaced apart from each other, and a gate electrode crossing the channel pattern and extending in a first direction. One of the pair of source/drain patterns includes a first semiconductor layer and a second semiconductor layer thereon. The first semiconductor layer is in contact with a first semiconductor pattern, which is one of the stacked semiconductor patterns. The largest widths of the first semiconductor pattern, the first semiconductor layer, and the second semiconductor layer in the first direction are a first width, a second width, a third width, respectively, and the second width is larger than the first width and smaller than the third width.

公开(公告)号：US20220246738A1

公开(公告)日：2022-08-04

申请号：US17472926

申请日：2021-09-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dohee Kim ,  Gyeom Kim ,  Jinbum Kim ,  Haejun Yu ,  Kyungin Choi ,  Kihyun Hwang ,  Seunghun Lee

IPC: H01L29/417 ,  H01L27/088

Abstract: An integrated circuit device includes a plurality of gate structures each including a gate line extending on a fin-type active region and insulation spacers on sidewalls of the gate line; a source/drain contact between first and second gate structures, and having opposing sides that are asymmetric in the first horizontal direction; and an insulation liner on sidewalls of the source/drain contact. The source/drain contact includes a lower contact portion and an upper contact portion having a horizontal extension that extends on an upper corner of the first gate structure, the insulation liner includes a first local region between the upper corner and the horizontal extension and a second local region that is farther from the substrate than the first local region, and a thickness of the first local region is greater than that of the second local region.

公开(公告)号：US10109747B2

公开(公告)日：2018-10-23

申请号：US14831449

申请日：2015-08-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byong-Hyun Jang ,  Juhyung Kim ,  Woonkyung Lee ,  Jaegoo Lee ,  Chaeho Kim ,  Junkyu Yang ,  Phil Ouk Nam ,  Jaeyoung Ahn ,  Kihyun Hwang

IPC: H01L29/792 ,  H01L29/66 ,  H01L29/423 ,  H01L29/04 ,  H01L29/10 ,  H01L23/528 ,  H01L29/51 ,  H01L27/11582 ,  H01L27/1157

Abstract: A semiconductor memory device and a method of fabricating the same. The device includes a plurality of gates vertically stacked on a top surface of a substrate with an epitaxial layer formed in the substrate, a vertical channel vertically penetrating the gates to be electrically connected to the epitaxial layer, and a memory layer provided between the vertical channel and the gates. The epitaxial layer has a top surface positioned at a level between a bottom surface of the lowermost one of the gates and the top surface of the substrate.

公开(公告)号：US09972638B2

公开(公告)日：2018-05-15

申请号：US14621568

申请日：2015-02-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunghae Lee ,  Daehong Eom ,  JinGyun Kim ,  Daehyun Jang ,  Kihyun Hwang ,  Seongsoo Lee ,  Kyunghyun Kim ,  Chadong Yeo ,  Jun-Youl Yang ,  Se-Ho Cha

IPC: H01L21/8238 ,  H01L27/11582 ,  H01L29/78 ,  H01L21/283 ,  H01L21/311 ,  H01L27/11556 ,  H01L29/66

CPC classification number: H01L27/11582 ,  H01L21/283 ,  H01L21/311 ,  H01L27/11556 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/7827

Abstract: Three dimensional semiconductor memory devices and methods of fabricating the same are provided. According to the method, sacrificial layers and insulating layers are alternately and repeatedly stacked on a substrate, and a cutting region penetrating an uppermost sacrificial layer of the sacrificial layers is formed. The cutting region is filled with a non sacrificial layer. The insulating layers and the sacrificial layers are patterned to form a mold pattern. The mold pattern includes insulating patterns, sacrificial patterns, and the non sacrificial layer in the cutting region. The sacrificial patterns may be replaced with electrodes. The related semiconductor memory device is also provided.

公开(公告)号：US09768266B2

公开(公告)日：2017-09-19

申请号：US14796569

申请日：2015-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang Soo Seol ,  Chanjin Park ,  Kihyun Hwang ,  Hanmei Choi ,  Sunghoi Hur ,  Wansik Hwang ,  Toshiro Nakanishi ,  Kwangmin Park ,  Juyul Lee

IPC: H01L29/423 ,  H01L21/3213 ,  H01L27/06 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/792 ,  H01L27/11582 ,  H01L29/51

CPC classification number: H01L29/42348 ,  H01L21/32137 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/511 ,  H01L29/517 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.