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公开(公告)号:US20170373062A1
公开(公告)日:2017-12-28
申请号:US15494769
申请日:2017-04-24
Applicant: Samsung Electronics Co., Ltd.
Inventor: Moon Seung Yang , Dong Chan SUH , Chul KIM , Woo Bin SONG , Ji Eon YOON , Seung Ryul LEE
IPC: H01L27/092 , H01L29/06 , H01L29/10 , H01L29/78
Abstract: The semiconductor device includes a first multi-channel active pattern protruding from a substrate, and having a first height, a second multi-channel active pattern on the substrate, being spaced apart from the substrate, and having a second height that is less than the first height, and a gate electrode on the substrate, intersecting the first multi-channel active pattern and the second multi-channel active pattern.
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公开(公告)号:US20170352759A1
公开(公告)日:2017-12-07
申请号:US15685459
申请日:2017-08-24
Applicant: Samsung Electronics Co., Ltd.
Inventor: Nam Kyu KIM , Dong Chan SUH , Kwan Heum LEE , Byeong Chan LEE , Cho Eun LEE , Su Jin JUNG , Gyeom KIM , Ji Eon YOON
IPC: H01L29/78 , H01L29/165 , H01L29/417 , H01L29/08
CPC classification number: H01L29/7848 , H01L29/0847 , H01L29/165 , H01L29/41766 , H01L29/7834
Abstract: A semiconductor device may include: a semiconductor substrate, a device isolating layer embedded within the semiconductor substrate and defining an active region, a channel region formed in the active region, a gate electrode disposed above the channel region, a gate insulating layer provided between the channel region and the gate electrode, and a silicon germanium epitaxial layer adjacent to the channel region within the active region and including a first epitaxial layer containing a first concentration of germanium, a second epitaxial layer containing a second concentration of germanium, higher than the first concentration, and a third epitaxial layer containing a third concentration of germanium, lower than the second concentration, the first to third epitaxial layers being sequentially stacked on one another in that order.
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公开(公告)号:US20170186609A1
公开(公告)日:2017-06-29
申请号:US15363139
申请日:2016-11-29
Applicant: Samsung Electronics Co., Ltd.
Inventor: Ji Eon YOON , Chul KIM , Sang Moon LEE , Seung Ryul LEE
CPC classification number: H01L21/02639 , H01L21/02381 , H01L21/02521 , H01L21/02532 , H01L21/02538 , H01L21/02598 , H01L21/02642 , H01L21/02647 , H01L21/0265 , H01L29/32
Abstract: A semiconductor single crystal structure may include a substrate; a defect trapping stack disposed on the substrate; and a semiconductor single crystal disposed on the defect trapping stack, and having a lattice mismatch with a crystal of the substrate, in which the defect trapping stack may include a first dielectric layer disposed on the substrate, and having at least one first opening, a second dielectric layer disposed on the first dielectric layer, and having at least one second opening, a third dielectric layer disposed on the second dielectric layer, and having at least one third opening, and a fourth dielectric layer disposed on the third dielectric layer, and having at least one fourth opening, and in which the semiconductor single crystal may extend to a region of the substrate defined in the at least one first opening through the at least one first to fourth opening.
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