公开(公告)号：US20220102497A1

公开(公告)日：2022-03-31

申请号：US17546326

申请日：2021-12-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Uk JANG ,  Seung Hun LEE ,  Su Jin JUNG ,  Young Dae CHO

IPC: H01L29/08 ,  H01L29/786 ,  H01L29/167 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423

Abstract: A semiconductor device including an active region defined in a substrate; at least one channel layer on the active region; a gate electrode intersecting the active region and on the active region and surrounding the at least one channel layer; and a pair of source/drain regions adjacent to both sides of the gate electrode, on the active region, and in contact with the at least one channel layer, wherein the pair of source/drain regions includes a selective epitaxial growth (SEG) layer, and a maximum width of each of the pair of source/drain regions in a first direction is 1.3 times or less a width of the active region in the first direction.

公开(公告)号：US20200152740A1

公开(公告)日：2020-05-14

申请号：US16386459

申请日：2019-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Uk JANG ,  Seung Hun LEE ,  Su Jin JUNG ,  Young Dae CHO

IPC: H01L29/08 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/417 ,  H01L29/167

Abstract: A semiconductor device including an active region defined in a substrate; at least one channel layer on the active region; a gate electrode intersecting the active region and on the active region and surrounding the at least one channel layer; and a pair of source/drain regions adjacent to both sides of the gate electrode, on the active region, and in contact with the at least one channel layer, wherein the pair of source/drain regions includes a selective epitaxial growth (SEG) layer, and a maximum width of each of the pair of source/drain regions in a first direction is 1.3 times or less a width of the active region in the first direction.

公开(公告)号：US20250022959A1

公开(公告)日：2025-01-16

申请号：US18901222

申请日：2024-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Uk JANG ,  Young Dae CHO ,  Ki Hwan KIM ,  Su Jin JUNG

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes an active region extending in a first direction on a substrate, channel layers on the active region and spaced apart vertically, a gate structure intersecting the active region and the channel layers, the gate structure extending in a second direction and surrounding the channel layers, and a source/drain region on the active region at a side of the gate structure, the source/drain region contacting the channel layers, the source/drain region including first epitaxial layers having a first composition and including first layers on side surfaces of the channel layers and a second layer on the active region at a lower end of the source/drain region, and a second epitaxial layer having a second composition different from the first composition, the second epitaxial layer being between the first epitaxial layers in the first direction and being between the first epitaxial layers vertically in a third direction.

公开(公告)号：US20230395668A1

公开(公告)日：2023-12-07

申请号：US18296329

申请日：2023-04-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Su Jin JUNG ,  Jin Bum KIM ,  In Gyu JANG

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/775 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/41733 ,  H01L29/0653 ,  H01L29/775 ,  H01L29/78696 ,  H01L29/66553 ,  H01L29/0673 ,  H01L29/42392

Abstract: A semiconductor device includes a substrate; an active pattern disposed on the substrate and extending in a first direction; a plurality of gate structures, wherein the plurality of gate structures is disposed on the active pattern and arranged in the first direction, wherein each of the plurality of gate structures includes a gate electrode and a gate insulating film, and wherein the gate electrode extends in a second direction; a source/drain pattern disposed between adjacent gate structures of the plurality of gate structures; a source/drain contact connected to the source/drain pattern; and a contact silicide film disposed between the source/drain pattern and the source/drain contact, wherein the contact silicide film includes a bowl region that wraps a lower portion of the source/drain contact, and a protruding region that protrudes from the bowl region of the contact silicide film.

公开(公告)号：US20230307545A1

公开(公告)日：2023-09-28

申请号：US18204469

申请日：2023-06-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Uk JANG ,  Young Dae CHO ,  Ki Hwan KIM ,  Su Jin JUNG

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L29/7851 ,  H01L29/0847 ,  H01L29/78696 ,  H01L29/42392

Abstract: A semiconductor device includes an active region extending in a first direction on a substrate, channel layers on the active region and spaced apart vertically, a gate structure intersecting the active region and the channel layers, the gate structure extending in a second direction and surrounding the channel layers, and a source/drain region on the active region at a side of the gate structure, the source/drain region contacting the channel layers, the source/drain region including first epitaxial layers having a first composition and including first layers on side surfaces of the channel layers and a second layer on the active region at a lower end of the source/drain region, and a second epitaxial layer having a second composition different from the first composition, the second epitaxial layer being between the first epitaxial layers in the first direction and being between the first epitaxial layers vertically in a third direction.

公开(公告)号：US20190296144A1

公开(公告)日：2019-09-26

申请号：US16162510

申请日：2018-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Su Jin JUNG ,  Jeong Ho YOO ,  Jong Ryeol YOO ,  Young Dae CHO

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/06 ,  H01L21/768 ,  H01L21/308 ,  H01L29/36

Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the device including an active pattern protruding from a substrate; a plurality of gate structures each including a gate electrode and crossing the active pattern; and a source/drain region between the plurality of gate structures, wherein the source/drain region includes a high concentration doped layer in contact with a bottom surface of a recessed region in the active pattern, a first epitaxial layer in contact with an upper surface of the high concentration doped layer and a sidewall of the recessed region, and a second epitaxial layer on the first epitaxial layer, and the high concentration doped layer has a first area in contact with the bottom surface of the recessed region and a second area in contact with the sidewall of the recessed region, the first area being wider than the second area.

公开(公告)号：US20170352759A1

公开(公告)日：2017-12-07

申请号：US15685459

申请日：2017-08-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nam Kyu KIM ,  Dong Chan SUH ,  Kwan Heum LEE ,  Byeong Chan LEE ,  Cho Eun LEE ,  Su Jin JUNG ,  Gyeom KIM ,  Ji Eon YOON

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/417 ,  H01L29/08

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/7834

Abstract: A semiconductor device may include: a semiconductor substrate, a device isolating layer embedded within the semiconductor substrate and defining an active region, a channel region formed in the active region, a gate electrode disposed above the channel region, a gate insulating layer provided between the channel region and the gate electrode, and a silicon germanium epitaxial layer adjacent to the channel region within the active region and including a first epitaxial layer containing a first concentration of germanium, a second epitaxial layer containing a second concentration of germanium, higher than the first concentration, and a third epitaxial layer containing a third concentration of germanium, lower than the second concentration, the first to third epitaxial layers being sequentially stacked on one another in that order.

公开(公告)号：US20240063306A1

公开(公告)日：2024-02-22

申请号：US18498901

申请日：2023-10-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Su Jin JUNG ,  Ki Hwan KIM ,  Sung Uk JANG ,  Young Dae CHO

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/78618 ,  H01L21/0259 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78696

Abstract: A semiconductor device is provided. The semiconductor comprises an active pattern including a lower pattern and a plurality of sheet patterns that are spaced apart from the lower pattern in a first direction, a source/drain pattern on the lower pattern and in contact with the plurality of sheet patterns, and a gate structure on opposing sides of the source/drain pattern in a second direction different from the first direction, the gate structure including a gate electrode on the plurality of sheet patterns, wherein the source/drain pattern includes an epitaxial region that comprises a semiconductor material and a cavity region that is inside the epitaxial region and that is surrounded by the semiconductor material.

公开(公告)号：US20220157990A1

公开(公告)日：2022-05-19

申请号：US17587402

申请日：2022-01-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Uk JANG ,  Ki Hwan KIM ,  Su Jin JUNG ,  Bong Soo KIM ,  Young Dae CHO

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/24

Abstract: A semiconductor device including an active region extending in a first direction on a substrate; a gate structure intersecting the active region and extending in a second direction on the substrate; and a source/drain region on the active region and at least one side of the gate structure, wherein the source/drain region includes a plurality of first epitaxial layers spaced apart from each other in the first direction, the plurality of first epitaxial layers including first impurities of a first conductivity type; and a second epitaxial layer filling a space between the plurality of first epitaxial layers, the second epitaxial layer including second impurities of the first conductivity type.

公开(公告)号：US20210296499A1

公开(公告)日：2021-09-23

申请号：US17337759

申请日：2021-06-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Uk JANG ,  Young Dae CHO ,  Ki Hwan KIM ,  Su Jin JUNG

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/786 ,  H01L29/423

Abstract: A semiconductor device includes an active region extending in a first direction on a substrate, channel layers on the active region and spaced apart vertically, a gate structure intersecting the active region and the channel layers, the gate structure extending in a second direction and surrounding the channel layers, and a source/drain region on the active region at a side of the gate structure, the source/drain region contacting the channel layers, the source/drain region including first epitaxial layers having a first composition and including first layers on side surfaces of the channel layers and a second layer on the active region at a lower end of the source/drain region, and a second epitaxial layer having a second composition different from the first composition, the second epitaxial layer being between the first epitaxial layers in the first direction and being between the first epitaxial layers vertically in a third direction.