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公开(公告)号：US10147650B2
公开(公告)日：2018-12-04
申请号：US15211200
申请日：2016-07-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sung-Min Kim , Ji-Su Kang , Byung-Chan Ryu , Jae-Hyun Park , Yu-Ri Lee , Dong-Ho Cha
IPC: H01L21/70 , H01L21/8238 , H01L29/78 , H01L29/08 , H01L29/161 , H01L29/16 , H01L29/165 , H01L27/092
Abstract: A semiconductor device includes a first fin-type pattern and a second fin-type pattern which protrude upwardly from an upper surface of a field insulating film and extend in a first direction. A gate structure intersects the first fin-type pattern and the second fin-type pattern. A first epitaxial layer is on the first fin-type pattern on at least one side of the gate structure, and a second epitaxial layer is on the second fin-type pattern on at least one side of the gate structure. A metal contact covers outer circumferential surfaces of the first epitaxial layer and the second epitaxial layer. The first epitaxial layer contacts the second epitaxial layer.
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公开(公告)号：US09448768B2
公开(公告)日：2016-09-20
申请号：US13792642
申请日：2013-03-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yong Ki Lee , Jonghoon Shin , KyoungMoon Ahn , Ji-Su Kang , Sun-Soo Shin
IPC: G06F7/72
Abstract: A modular multiplier and a modular multiplication method are provided. The modular multiplier includes: a first register which stores a previous accumulation value calculated at a previous cycle; a second register which stores a previous quotient calculated at the previous cycle; a quotient generator which generates a quotient using the stored previous accumulation value output from the first register; and an accumulator which receives an operand, a bit value of a multiplier, the stored previous accumulation value, and the stored previous quotient to calculate an accumulation value in a current cycle, wherein the calculated accumulation value is updated to the first register, and the generated quotient is updated to the second register.
Abstract translation: 提供了一种模数乘法器和一种模乘法。 模数乘法器包括：第一寄存器，其存储在先前周期计算的先前累积值; 存储在前一周期计算的先前商的第二寄存器; 商产生器，其使用从所述第一寄存器输出的存储的先前累积值生成商; 以及累加器，其接收操作数，乘数的位值，存储的先前累积值和存储的先前商，以计算当前周期中的累积值，其中计算的累加值被更新为第一寄存器，并且 生成商被更新到第二个寄存器。
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3.发明授权公开(公告)号：US09164732B2
公开(公告)日：2015-10-20
申请号：US14139113
申请日：2013-12-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yong Ki Lee , Sun-Soo Shin , Jonghoon Shin , Kyoung Moon Ahn , Ji-Su Kang , Kee Moon Chun
CPC classification number: G06F7/722 , G06F7/728 , H04L9/3013 , H04L9/302
Abstract: A multiplication method and a modular multiplier are provided. The multiplication method includes transforming a redundant-form multiplier by adding a recoding constant to the multiplier, performing recoding by using the transformed multiplier, and performing partial multiplication between the multiplier and a multiplicand using result values of the recoding.
Abstract translation: 提供乘法和模乘法。 乘法方法包括：通过向乘法器添加重新编码常数来变换冗余形式乘法器，通过使用变换乘数执行重新编码，并且使用重新编码的结果值，在乘法器和乘法器之间执行部分乘法。
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公开(公告)号：US11070380B2
公开(公告)日：2021-07-20
申请号：US15212343
申请日：2016-07-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kitak Kim , Ji-Su Kang , Kiseok Bae , Jonghoon Shin , Kyoungmoon Ahn , Jinsu Hyun
Abstract: An authentication apparatus, included in a device supporting a network communication, includes a certificate handler that receives a certificate of an opponent and parses or verifies the certificate of the opponent. Cryptographic primitives receive an authentication request of the opponent, generate a random number in response to the authentication request, generate a challenge corresponding to the random number, and verify a response of the opponent corresponding to the challenge. A shared memory stores the parsed certificate, the random number, the challenge, and the response. An authentication controller controls the certificate handler, the cryptographic primitives, and the shared memory through a register setting, according to an authentication protocol.
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公开(公告)号：US09841950B2
公开(公告)日：2017-12-12
申请号：US15242768
申请日：2016-08-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yong Ki Lee , Jonghoon Shin , KyoungMoon Ahn , Ji-Su Kang , Sun-Soo Shin
IPC: G06F7/72
Abstract: A modular multiplier and a modular multiplication method are provided. The modular multiplier includes: a first register which stores a previous accumulation value calculated at a previous cycle; a second register which stores a previous quotient calculated at the previous cycle; a quotient generator which generates a quotient using the stored previous accumulation value output from the first register; and an accumulator which receives an operand, a bit value of a multiplier, the stored previous accumulation value, and the stored previous quotient to calculate an accumulation value in a current cycle, wherein the calculated accumulation value is updated to the first register, and the generated quotient is updated to the second register.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20130262544A1
公开(公告)日：2013-10-03
申请号：US13716994
申请日：2012-12-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yong-Ki Lee , Jong-Hoon Shin , Kyoung-Moon Ahn , Ji-Su Kang , Sun-Soo Shin
CPC classification number: G06F7/533 , G06F7/5324 , G06F7/5338 , G06F7/588 , G06F2207/7257
Abstract: An electronic multiplier, such as a multiplication circuit, may include a partial product generator, a Booth code encoder and an accumulator. The partial product generator may generate partial product data based on a Booth code and multiplicand data. The Booth code encoder may generate the Booth code based on multiplier data. The Booth code may include a zero-generation Booth code and a zero-avoidance Booth code. The Booth code encoder may selectively generate the zero-generation Booth code or the zero-avoidance Booth code when the partial product data correspond to a partial product of zero. The accumulator accumulates the partial product data to provide a multiplication result of the multiplicand data and the multiplier data.
Abstract translation: 诸如乘法电路的电子倍增器可以包括部分乘积发生器，布斯码编码器和累加器。 部分积发生器可以基于布斯码和被乘数数据生成部分乘积数据。 布斯码编码器可以基于乘数数据生成布斯码。 展位代码可以包括零代布斯代码和零回避布斯码。 当部分乘积数据对应于零的部分乘积时，布斯克编码器可以选择性地生成零代布斯码或零回避布斯码。 累加器积累部分乘积数据以提供被乘数数据和乘数数据的相乘结果。
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公开(公告)号：US10693625B2
公开(公告)日：2020-06-23
申请号：US15485857
申请日：2017-04-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ji-Su Kang , Kyoung-Moon Ahn , Yong-Ki Lee , Ki-Seok Bae
Abstract: An application processor includes a security processor. An operating method of the security processor includes generating a recoder input including a digit-unit multiplier and a reference bit. At least one random bits having a random value are generated. When the recoder input has a predetermined pattern, the recoder input is converted into a first recoding value or a second recoding value according to a random bit corresponding to the recoder input to generate a recoding result.
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公开(公告)号：US20190051566A1
公开(公告)日：2019-02-14
申请号：US16162428
申请日：2018-10-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sung-Min Kim , Ji-Su Kang , Byung-Chan Ryu , Jae-Hyun Park , Yu-Ri Lee , Dong-Ho Cha
IPC: H01L21/8238 , H01L29/16 , H01L29/78 , H01L29/165 , H01L29/161 , H01L29/08 , H01L27/092
Abstract: A semiconductor device includes a first fin-type pattern and a second fin-type pattern which protrude upwardly from an upper surface of a field insulating film and extend in a first direction. A gate structure intersects the first fin-type pattern and the second fin-type pattern. A first epitaxial layer is on the first fin-type pattern on at least one side of the gate structure, and a second epitaxial layer is on the second fin-type pattern on at least one side of the gate structure. A metal contact covers outer circumferential surfaces of the first epitaxial layer and the second epitaxial layer. The first epitaxial layer contacts the second epitaxial layer.
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公开(公告)号：US09098381B2
公开(公告)日：2015-08-04
申请号：US13734520
申请日：2013-01-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyoungmoon Ahn , Jonghoon Shin , Yong Ki Lee , Ji-Su Kang , Sun-Soo Shin
IPC: G06F7/72
Abstract: A modular arithmetic unit includes a first input generator receiving first data to generate a first operand; a second input generator receiving second data to generate a second operand; an accumulator performing an accumulate/shift operation to add the first and second operands and outputting the carry and sum; a carry propagation adder adding the carry and the sum to output a result; and a data handler receiving either external data or the result and outputting the first data and the second data.
Abstract translation: 模块运算单元包括接收第一数据以产生第一操作数的第一输入发生器; 接收第二数据以产生第二操作数的第二输入发生器; 累加器执行累加/移位操作以添加第一和第二操作数并输出进位和和; 一个进位传播加法器，加上进位和和输出一个结果; 以及接收外部数据或结果并输出第一数据和第二数据的数据处理器。
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公开(公告)号：US11309048B2
公开(公告)日：2022-04-19
申请号：US17027007
申请日：2020-09-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hong-Mook Choi , Hye Soo Lee , Ji-Su Kang , Hyun Il Kim
Abstract: A method of testing using a memory test apparatus connected to a memory device includes receiving a test command. When the test command is a finite state machine (FSM) operation command, the memory device is tested in accordance with the FSM operation command, and an operation is performed to output a result depending on a pass/fail result. But, when the test command is a direct access command, an auto-operation test of input data is performed in a test region according to received address information, and a test result is output, which may include output data with fail information or the auto-operation.
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