公开(公告)号：US12272652B2

公开(公告)日：2025-04-08

申请号：US18140985

申请日：2023-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiwon Shin ,  Donguk Kwon ,  Kwang Bok Woo ,  Minseung Ji

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/367 ,  H01L25/065

Abstract: A semiconductor package includes a first sub-semiconductor device, an interposer, and a second sub-semiconductor device stacked on each other, and a heat sink covering the second sub-semiconductor device. The first sub-semiconductor device includes a first substrate and a first semiconductor chip. The interposer includes a dielectric layer, a thermal conductive layer in contact with a bottom surface of the dielectric layer, a first thermal conductive pad in contact with a top surface of the dielectric layer, and thermal conductive vias penetrating the dielectric layer to connect the thermal conductive layer to the first thermal conductive pad. A bottom surface of the thermal conductive layer is adjacent to and connected to a top surface of the first semiconductor chip. The second sub-semiconductor device is disposed on the dielectric layer without overlapping the first thermal conductive pad. The heat sink further covers the first thermal conductive pad to be connected thereto.

公开(公告)号：US12288745B2

公开(公告)日：2025-04-29

申请号：US17844815

申请日：2022-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donguk Kwon ,  Wooram Myung ,  Jiwon Shin ,  Pilsung Choi

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/48 ,  H01L25/10

Abstract: A semiconductor package includes a lower substrate having a chip mounting region, an interconnection region surrounding the chip mounting region, and an outer region surrounding the interconnection region, and includes a lower wiring layer. A first solder resist pattern has first openings exposing bonding regions of the lower wiring layer. A semiconductor chip is on the chip mounting region and is electrically connected to the lower wiring layer. A second solder resist pattern is on the first solder resist pattern on the interconnection and outer regions and is spaced apart from the semiconductor chip, and includes second openings disposed on the first openings. An upper substrate covers the semiconductor chip, and includes an upper wiring layer. A vertical connection structure is on the interconnection region and electrically connects the upper and lower wiring layers. A solder resist spacer is on the second solder resist pattern on the outer region.

公开(公告)号：US11676904B2

公开(公告)日：2023-06-13

申请号：US17328297

申请日：2021-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiwon Shin ,  Donguk Kwon ,  Kwang Bok Woo ,  Minseung Ji

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L23/367

CPC classification number: H01L23/5385 ,  H01L23/367 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48147 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06506 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2924/15156 ,  H01L2924/15311 ,  H01L2924/3511

Abstract: A semiconductor package includes a first sub-semiconductor device, an interposer, and a second sub-semiconductor device stacked on each other, and a heat sink covering the second sub-semiconductor device. The first sub-semiconductor device includes a first substrate and a first semiconductor chip. The interposer includes a dielectric layer, a thermal conductive layer in contact with a bottom surface of the dielectric layer, a first thermal conductive pad in contact with a top surface of the dielectric layer, and thermal conductive vias penetrating the dielectric layer to connect the thermal conductive layer to the first thermal conductive pad. A bottom surface of the thermal conductive layer is adjacent to and connected to a top surface of the first semiconductor chip. The second sub-semiconductor device is disposed on the dielectric layer without overlapping the first thermal conductive pad. The heat sink further covers the first thermal conductive pad to be connected thereto.

公开(公告)号：US20250118565A1

公开(公告)日：2025-04-10

申请号：US18808273

申请日：2024-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunho Chu ,  Jiwon Shin ,  Kwangyong Lee ,  Minwoo Jeon

IPC: H01L21/3065 ,  H01L21/683 ,  H01L21/78

Abstract: A method of manufacturing a semiconductor chip includes grinding a substrate that includes a device region and a scribe lane region, forming a protective coating layer on the substrate, plasma-thinning the substrate, and plasma-sawing the scribe lane region of the substrate. The plasma-thinning of the substrate and the plasma-sawing of the scribe lane region of the substrate are performed in-situ in a same chamber.

公开(公告)号：US11749592B2

公开(公告)日：2023-09-05

申请号：US17348936

申请日：2021-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donguk Kwon ,  Jiwon Shin ,  Kwangbok Woo ,  Minseung Ji

IPC: H01L23/498 ,  H01L23/32 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L23/49833 ,  H01L23/3121 ,  H01L23/32 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/32227 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1058

Abstract: A lower semiconductor package of a package-on-package type semiconductor package includes: a package substrate; a semiconductor chip mounted on the package substrate; a chip connecting terminal disposed between the semiconductor chip and the package substrate and configured to connect the semiconductor chip to the package substrate; conductive pillars arranged on the package substrate to at least partially surround the semiconductor chip; and a dam structure configured to cover the conductive pillars on the package substrate and having a first opening at least partially surrounding the semiconductor chip.