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公开(公告)号：US10303197B2
公开(公告)日：2019-05-28
申请号：US15870252
申请日：2018-01-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seung-hyun Oh , Woo-jin Jang , Jong-woo Lee
Abstract: A reference voltage circuit is provided. The reference voltage circuit includes a first current bias circuit including a first node; a second current bias circuit including a plurality of NMOS transistors and a second node, and an amplifier configured to output a reference voltage having same value as the second voltage. The plurality of NMOS transistors include a first NMOS transistor and a second NMOS transistor, the first NMOS transistor is connected to the first node, and the plurality of NMOS transistors are connected to the second node and configured to perform a sub-threshold operation based on a first voltage of the first node so that a second voltage is generated at the second node.
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公开(公告)号：US09893738B2
公开(公告)日：2018-02-13
申请号：US15469712
申请日：2017-03-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jae-hoon Lee , Seung-hyun Oh , Jong-woo Lee
CPC classification number: H03M1/1245 , G11C27/02 , G11C27/024 , H03M1/08 , H03M1/468
Abstract: An analog-to-digital converter includes a sample hold circuit configured to receive an analog input signal based on an operating mode, the operating mode being one of at least two modes including a sample mode and a hold mode. The sample hold circuit includes a first transistor including a control terminal and a first terminal, the first transistor configured to receive a control signal via the control terminal and receive the analog input signal via the first terminal. The analog-to-digital converter further includes a bootstrap switch operationally connected to the control terminal and the first terminal of the first transistor, the bootstrap switch configured to form a first current path from a power source based on the analog input signal and a boosted voltage of the control terminal of the first transistor in the sample mode, the control terminal bing along the first current path in the sample mode.
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公开(公告)号：US10951445B2
公开(公告)日：2021-03-16
申请号：US16191611
申请日：2018-11-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Barosaim Sung , Chilun Lo , Jae-hoon Lee , Jong-woo Lee , Seung-hyun Oh
Abstract: A radio frequency (RF) integrated circuit is provided. The RF integrated circuit supports carrier aggregation and includes first receiving circuits and a first shared phase locked loop circuit that provides a first frequency signal of a first frequency to the first receiving circuits. One of the first receiving circuits includes an analog to digital converter (ADC) and a digital conversion circuit. The ADC converts an RF signal received by the one of the first receiving circuits to a digital signal by using the first frequency signal. The digital conversion circuit generates a digital baseband signal by performing frequency down conversion on the digital signal.
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公开(公告)号：US20200177213A1
公开(公告)日：2020-06-04
申请号：US16779763
申请日：2020-02-03
Applicant: SAMSUNG ELECTRONICS CO,, LTD.
Inventor： SEUNG-HYUN OH , Chilun Lo , Barosaim Sung , Jae-hoon Lee , Jong-woo Lee
Abstract: Provided are a radio-frequency integrated chip (RFIC) and a wireless communication device including the RFIC. An RFIC configured to receive a carrier aggregated receive signal having at least first and second carrier signals may include first and second carrier receivers configured to generate, from the receive signal, first and second digital carrier signals, respectively. A phase-locked loop (PLL) may output a first frequency signal having a first frequency to the first carrier receiver and the second carrier receiver. The first and second carrier receivers may include first and second analog mixers, respectively, for translating frequencies of the receive signal, using the first frequency signal and the second frequency signal, respectively. Each of the first and second carrier receivers may further include a digital mixer for further translating the frequencies of the receive signal in the digital domain.
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公开(公告)号：US20190025867A1
公开(公告)日：2019-01-24
申请号：US15870252
申请日：2018-01-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seung-hyun Oh , Woo-jin Jang , Jong-woo Lee
Abstract: A reference voltage circuit is provided. The reference voltage circuit includes a first current bias circuit including a first node; a second current bias circuit including a plurality of NMOS transistors and a second node, and an amplifier configured to output a reference voltage having same value as the second voltage. The plurality of NMOS transistors include a first NMOS transistor and a second NMOS transistor, the first NMOS transistor is connected to the first node, and the plurality of NMOS transistors are connected to the second node and configured to perform a sub-threshold operation based on a first voltage of the first node so that a second voltage is generated at the second node.
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Patent Agency Ranking
公开(公告)号：US10110248B2
公开(公告)日：2018-10-23
申请号：US15702962
申请日：2017-09-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jae-hoon Lee , Jong-woo Lee , Chilun Lo , Seung-hyun Oh , Jong-mi Lee
IPC: H03M3/00
Abstract: A variable feedback gain delta modulator includes group of capacitors commonly connected to a first terminal and are respectively classified into a first capacitor group and a second capacitor group; a comparator for sequentially generating n-bit digital output signals based on a voltage of the first terminal; and a switch group including switches respectively connected to the capacitors, wherein the switches are respectively classified into a first switch group and a second switch group respectively connected to the first capacitor group and the second capacitor group, and the first switch group and the second switch group respectively operate according to a first control signal and a second control signal that are determined based on the n-bit digital output signals and the variable feedback gain.
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公开(公告)号：US20190007057A1
公开(公告)日：2019-01-03
申请号：US16104414
申请日：2018-08-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jae-Hoon Lee , Jong-woo Lee , Chilun Lo , Seung-hyun Oh , Jong-mi Lee
IPC: H03M3/00
Abstract: A variable feedback gain delta modulator includes group of capacitors commonly connected to a first terminal and are respectively classified into a first capacitor group and a second capacitor group; a comparator for sequentially generating n-bit digital output signals based on a voltage of the first terminal; and a switch group including switches respectively connected to the capacitors, wherein the switches are respectively classified into a first switch group and a second switch group respectively connected to the first capacitor group and the second capacitor group, and the first switch group and the second switch group respectively operate according to a first control signal and a second control signal that are determined based on the n-bit digital output signals and the variable feedback gain.
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8.发明授权Image forming apparatus and method to determine an operation start time point of a photoconductor driving unit 有权用于确定感光体驱动单元的操作开始时间点的图像形成装置和方法公开(公告)号：US09170540B2
公开(公告)日：2015-10-27
申请号：US14567395
申请日：2014-12-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Shinichi Hisatomi , So-won Sheen , Jong-woo Lee , Seok-hoon Choi
IPC: G03G15/00
CPC classification number: G03G15/5008 , G03G15/0189 , G03G2215/0132
Abstract: An image forming apparatus and a method of controlling the image forming apparatus are provided. An image forming apparatus may determine the operation start time point of a photoconductor based on ready times of the photoconductor and devices used in image forming processes so as to minimize idling of the photoconductor.
Abstract translation: 提供了图像形成装置和控制图像形成装置的方法。 图像形成装置可以基于光电导体的准备时间和图像形成处理中使用的装置来确定感光体的操作开始时间点，以便最小化感光体的怠速。
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公开(公告)号：US20150160597A1
公开(公告)日：2015-06-11
申请号：US14567395
申请日：2014-12-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Shinichi Hisatomi , So-won Sheen , Jong-woo Lee , Seok-hoon Choi
IPC: G03G15/00
CPC classification number: G03G15/5008 , G03G15/0189 , G03G2215/0132
Abstract: An image forming apparatus and a method of controlling the image forming apparatus are provided. An image forming apparatus may determine the operation start time point of a photoconductor based on ready times of the photoconductor and devices used in image forming processes so as to minimize idling of the photoconductor.
Abstract translation: 提供了图像形成装置和控制图像形成装置的方法。 图像形成装置可以基于光电导体的准备时间和图像形成处理中使用的装置来确定感光体的操作开始时间点，以便最小化感光体的怠速。
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公开(公告)号：US11031962B2
公开(公告)日：2021-06-08
申请号：US16779763
申请日：2020-02-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seung-hyun Oh , Chilun Lo , Barosaim Sung , Jae-hoon Lee , Jong-woo Lee
Abstract: Provided are a radio-frequency integrated chip (RFIC) and a wireless communication device including the RFIC. An RFIC configured to receive a carrier aggregated receive signal having at least first and second carrier signals may include first and second carrier receivers configured to generate, from the receive signal, first and second digital carrier signals, respectively. A phase-locked loop (PLL) may output a first frequency signal having a first frequency to the first carrier receiver and the second carrier receiver. The first and second carrier receivers may include first and second analog mixers, respectively, for translating frequencies of the receive signal, using the first frequency signal and the second frequency signal, respectively. Each of the first and second carrier receivers may further include a digital mixer for further translating the frequencies of the receive signal in the digital domain.
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