公开(公告)号：US20210098483A1

公开(公告)日：2021-04-01

申请号：US16890500

申请日：2020-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seogoo KANG ,  Daehyun JANG ,  Jaeryong SIM ,  Jongseon AHN ,  Jeehoon HAN

IPC: H01L27/11575 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11548

Abstract: A semiconductor device includes a peripheral circuit region including a first substrate and circuit elements on the first substrate; and a memory cell region including a second substrate on an upper portion of the first substrate, gate electrodes spaced apart from each other and vertically stacked on the second substrate, channel structures extending vertically through the gate electrodes to the second substrate, first separation regions penetrating through the gate electrodes between the channel structures and extending in one direction, and a second separation region extending vertically to penetrate through the second substrate from above and having a bent portion due to a change in width.

公开(公告)号：US20250017018A1

公开(公告)日：2025-01-09

申请号：US18640811

申请日：2024-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seongjae GO ,  Duyoung YANG ,  Kangmin KIM ,  Jongseon AHN ,  Byeongin CHOE

IPC: H10B43/35 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27

Abstract: A semiconductor device includes a plate layer; gate electrodes stacked and spaced apart from each other on the plate layer and including first gate electrodes and a second gate electrode on the first gate electrodes; first channel structures extending in the first gate electrodes; and second channel structures extending in the second gate electrode and electrically connected to the first channel structures, respectively, wherein the second gate electrode includes a metal material, and wherein each of the second channel structures includes a second channel layer, a second gate dielectric layer between the second channel layer and the second gate electrode, a second channel buried insulating layer on an internal side surface of the second channel layer, a second channel pad on the second channel buried insulating layer, and a second pad oxide layer on the second channel pad and the second channel layer.

公开(公告)号：US20240130123A1

公开(公告)日：2024-04-18

申请号：US18208459

申请日：2023-06-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yejin PARK ,  Seung Yoon KIM ,  Heesuk KIM ,  Hyeongjin KIM ,  Sehee JANG ,  Minsoo SHIN ,  Seungjun SHIN ,  Sanghun CHUN ,  Jeehoon HAN ,  Jae-Hwang SIM ,  Jongseon AHN

IPC: H10B43/27 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  H10B80/00

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L23/5283 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06541

Abstract: Disclosed are semiconductor devices, electronic systems including the same, and methods of fabricating the same. The semiconductor device comprises a first gate stack structure including a first dielectric pattern and a first conductive pattern that are alternately stacked with each other, a memory channel structure including a first memory portion that penetrates the first gate stack structure, a through contact including a first through portion at a level the same as a level of the first memory portion, and a connection contact including a first connection portion at a level the same as the level of the first memory portion and the level of the first through portion. A minimum width of the first memory portion is less than a minimum width of the first through portion and a minimum width of the first connection portion.

公开(公告)号：US20210043568A1

公开(公告)日：2021-02-11

申请号：US16876600

申请日：2020-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung HYUN ,  Dongug KO ,  Joohee PARK ,  Juhak SONG ,  Jongseon AHN ,  Sungwon CHO

IPC: H01L23/535 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: A vertical semiconductor device may include may include a substrate, a stacked structure, an insulating interlayer, a buffer pattern and a first contact plug. The stacked structure may include insulation patterns and conductive patterns stacked on each other on the substrate. The conductive patterns may extend in a first direction parallel to an upper surface of the substrate, and edges of the conductive patterns may have a staircase shape. The conductive patterns may include pad patterns defined by exposed upper surfaces of the conductive patterns. The insulating interlayer may cover the stacked structure. The buffer pattern may be on the insulating interlayer. The first contact plug may pass through the buffer pattern and the insulating interlayer. The first contact plug may contact one of the pad patterns. The buffer pattern may reduce defects from forming the first contact plug.

公开(公告)号：US20250089252A1

公开(公告)日：2025-03-13

申请号：US18820966

申请日：2024-08-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongseon AHN ,  Hyunju KIM ,  Jaehwang SIM ,  Seulbi LEE

IPC: H10B43/27

Abstract: A semiconductor device includes a gate electrode structure, a memory channel structure, and a contact plug. The gate electrode structure includes gate electrodes sequentially stacked and spaced apart from each other on a substrate in a first direction perpendicular to an upper surface of the substrate. Each of the gate electrodes extends in a second direction substantially parallel to the upper surface of the substrate. The memory channel structure extends through the gate electrode structure. The contact plug extends partially through the gate electrode structure to contact an upper surface of a first gate electrode among the gate electrodes. The contact plug is electrically insulated from a second gate electrode that is over the first gate electrode. At least a portion of the contact plug has a width decreasing from a top toward a bottom thereof in the first direction in a stepwise manner.

公开(公告)号：US20240276719A1

公开(公告)日：2024-08-15

申请号：US18379849

申请日：2023-10-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heesuk KIM ,  Seungyoon KIM ,  Yejin PARK ,  Inhwan BAEK ,  Jongseon AHN

IPC: H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device includes: a lower circuit pattern disposed on a substrate; a common source plate (CSP) disposed on the lower circuit pattern; a channel connection pattern disposed on the CSP; a sacrificial layer structure disposed on the CSP and spaced apart from the channel connection pattern; a support layer disposed on the channel connection pattern and the sacrificial layer structure; first and second gate electrode structures including gate electrodes stacked on the support layer and spaced apart from each other; a first channel disposed on the CSP, wherein the first channel extends through the first gate electrode structure, the support layer and the channel connection pattern; and a contact plug extending through the second gate electrode structure, the support layer, the sacrificial layer structure and the CSP, wherein the contact plug is electrically connected to the lower circuit pattern.

公开(公告)号：US20240090219A1

公开(公告)日：2024-03-14

申请号：US18231284

申请日：2023-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongseon AHN ,  Seungyoon Kim ,  Heesuk Kim ,  Yejin Park ,  Jaehwang Sim

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40

Abstract: A vertical memory device includes: a lower pad pattern disposed on a substrate; a cell stack structure disposed on the lower pad pattern and including first insulation layers and gate patterns, wherein the cell stack structure has a stepped shape; a through cell contact including a first through portion and a first protrusion, wherein the first through portion passes through a portion of the cell stack structure, and wherein the first protrusion protrudes from the first through portion and contacts an uppermost gate pattern of the gate patterns; and a first insulation pattern at least partially surrounding a sidewall, of the first through portion, that is below the first protrusion, wherein the first insulation pattern is longer than the first protrusion in a horizontal direction from the first through portion, and wherein a vertical thickness of the first protrusion is greater than a vertical thickness of the uppermost gate pattern.