公开(公告)号：US11538782B2

公开(公告)日：2022-12-27

申请号：US17108140

申请日：2020-12-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jubin Seo ,  Sujeong Park ,  Kwangjin Moon ,  Myungjoo Park

IPC: H01L23/00

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, an under-bump pattern on the semiconductor substrate and including a first metal, a bump pattern on the under-bump pattern, and an organic dielectric layer on the semiconductor substrate and in contact with a sidewall of the bump pattern. The bump pattern includes a support pattern in contact with the under-bump pattern and having a first width, and a solder pillar pattern on the support pattern and having a second width. The first width is greater than the second width. The support pattern includes at least one of a solder material and an intermetallic compound (IMC). The intermetallic compound includes the first metal and the solder material.

公开(公告)号：US12249558B2

公开(公告)日：2025-03-11

申请号：US18341087

申请日：2023-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jubin Seo ,  Kwangjin Moon ,  Kunsang Park ,  Myungjoo Park ,  Sujeong Park ,  Jaewon Hwang

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532 ,  H01L23/538 ,  H01L25/065

Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface, which are opposite to each other, an active pattern protruding from the first surface of the semiconductor substrate, the active pattern including a source/drain region, a power rail electrically connected to the source/drain region, a power delivery network disposed on the second surface of the semiconductor substrate, and a penetration via structure penetrating the semiconductor substrate and electrically connected to the power rail and the power delivery network. The penetration via structure includes a first conductive pattern electrically connected to the power rail and a second conductive pattern electrically connected to the power delivery network. The first conductive pattern includes a material different from the second conductive pattern.

公开(公告)号：US11887957B2

公开(公告)日：2024-01-30

申请号：US18076529

申请日：2022-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jubin Seo ,  Sujeong Park ,  Kwangjin Moon ,  Myungjoo Park

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/13099 ,  H01L2924/014 ,  H01L2924/3651

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, an under-bump pattern on the semiconductor substrate and including a first metal, a bump pattern on the under-bump pattern, and an organic dielectric layer on the semiconductor substrate and in contact with a sidewall of the bump pattern. The bump pattern includes a support pattern in contact with the under-bump pattern and having a first width, and a solder pillar pattern on the support pattern and having a second width. The first width is greater than the second width. The support pattern includes at least one of a solder material and an intermetallic compound (IMC). The intermetallic compound includes the first metal and the solder material.

公开(公告)号：US11728245B2

公开(公告)日：2023-08-15

申请号：US17316970

申请日：2021-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jubin Seo ,  Kwangjin Moon ,  Kunsang Park ,  Myungjoo Park ,  Sujeong Park ,  Jaewon Hwang

IPC: H01L23/528 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/481 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/53209 ,  H01L24/08 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/08146 ,  H01L2224/08147 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface, which are opposite to each other, an active pattern protruding from the first surface of the semiconductor substrate, the active pattern including a source/drain region, a power rail electrically connected to the source/drain region, a power delivery network disposed on the second surface of the semiconductor substrate, and a penetration via structure penetrating the semiconductor substrate and electrically connected to the power rail and the power delivery network. The penetration via structure includes a first conductive pattern electrically connected to the power rail and a second conductive pattern electrically connected to the power delivery network. The first conductive pattern includes a material different from the second conductive pattern.

公开(公告)号：US10049997B2

公开(公告)日：2018-08-14

申请号：US15440621

申请日：2017-02-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Il Choi ,  Hyoju Kim ,  Kwangjin Moon ,  Sujeong Park ,  Jubin Seo ,  Naein Lee ,  Ho-Jin Lee

IPC: H01L23/00

Abstract: A pad is disposed on a substrate. A bump structure is disposed on the pad and electrically connected to the pad. The bump structure includes a first copper layer and a second copper layer sequentially stacked on the pad and a solder ball on the second copper layer. A first X-ray diffraction (XRD) peak intensity ratio of (111) plane to (200) plane of the first copper layer is greater than a second XRD peak intensity ratio of (111) plane to (200) plane of the second copper layer.

公开(公告)号：US10020273B2

公开(公告)日：2018-07-10

申请号：US15345614

申请日：2016-11-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-il Choi ,  Hyoju Kim ,  Byunglyul Park ,  Yeun-Sang Park ,  Jubin Seo ,  Atsushi Fujisaki

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L25/0657 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05166 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13025 ,  H01L2224/13026 ,  H01L2224/13076 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13211 ,  H01L2224/13239 ,  H01L2224/16145 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/0105 ,  H01L2924/01327 ,  H01L2224/1146 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/01029

Abstract: According to aspects provided herein, a semiconductor device may include a bump providing improved reliability and reduced size. In some aspects, a conductive pad may be formed on a substrate, and a conductive support layer, which may be a pillar, may be formed on the conductive pad. An intermetallic compound (IMC) layer may be formed on the conductive support layer, and a solder layer may be formed on the IMC layer. In some aspects, the conductive support layer may be of a smaller width than the IMC layer. In some aspects, the conductive support layer may have side surfaces which are wider at the solder side than at the conductive pad side. In some aspects, other layers may be formed, such as a seed layer between the conductive pad and the conductive support layer, or a barrier layer between the conductive support layer and the IMC layer.