公开(公告)号：US09780052B2

公开(公告)日：2017-10-03

申请号：US14853807

申请日：2015-09-14

申请人： Micron Technology, Inc.

发明人： Giorgio Mariottini ,  Sameer Vadhavkar ,  Wayne Huang ,  Anilkumar Chandolu ,  Mark Bossler

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L21/00 ,  H01L23/00

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02126 ,  H01L2224/02135 ,  H01L2224/0219 ,  H01L2224/03013 ,  H01L2224/0346 ,  H01L2224/03472 ,  H01L2224/0361 ,  H01L2224/03906 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05082 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05184 ,  H01L2224/05547 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/05565 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/05687 ,  H01L2224/10145 ,  H01L2224/114 ,  H01L2224/11472 ,  H01L2224/13018 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/94 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2924/3651 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/053

摘要： The present technology is directed to manufacturing collars for under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects and associated systems. A semiconductor die includes a semiconductor material having solid-state components and an interconnect extending at least partially through the semiconductor material. An under-bump metal (UBM) structure is formed over the semiconductor material and is electrically coupled to corresponding interconnects. A collar surrounds at least a portion of the side surface of the UBM structure, and a solder material is disposed over the top surface of the UBM structure.

公开(公告)号：US09620468B2

公开(公告)日：2017-04-11

申请号：US14074637

申请日：2013-11-07

申请人： TONGFU MICROELECTRONICS CO., LTD.

发明人： Chang-Ming Lin ,  Yu-Juan Tao

IPC分类号： H01L21/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/525

CPC分类号： H01L24/13 ,  H01L23/3192 ,  H01L23/525 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03612 ,  H01L2224/03614 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11825 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/11903 ,  H01L2224/11906 ,  H01L2224/1191 ,  H01L2224/13024 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13541 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/81191 ,  H01L2924/12042 ,  H01L2924/3651 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/01049 ,  H01L2924/00

摘要： Various embodiments provide semiconductor packaging structures and methods for forming the same. In an exemplary method, a chip having a metal interconnect structure thereon can be provided. An insulating layer can be formed on the chip to expose the metal interconnect structure. A columnar electrode can be formed on the metal interconnect structure. A portion of the metal interconnect structure surrounding a bottom of the columnar electrode can be exposed. A diffusion barrier layer can be formed on sidewalls and a top surface of the columnar electrode, and on the exposed portion of the metal interconnect structure surrounding the bottom of the columnar electrode. A solder ball can then be formed on the diffusion barrier layer. The solder ball can wrap at least the sidewalls and the top surface of the columnar electrode.

公开(公告)号：US20170084564A1

公开(公告)日：2017-03-23

申请号：US15369815

申请日：2016-12-05

申请人： Intel Corporation

发明人： Valery M. DUBIN ,  Sridhar BALAKRISHNAN ,  Mark BOHR

IPC分类号： H01L23/00 ,  H01L21/48

CPC分类号： H01L24/13 ,  H01L21/288 ,  H01L21/4853 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11614 ,  H01L2224/13026 ,  H01L2224/13084 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13564 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/29111 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/35121 ,  H01L2924/3651 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.

公开(公告)号：US09508666B2

公开(公告)日：2016-11-29

申请号：US14045578

申请日：2013-10-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Kuo-Ching Hsu ,  Cheng-Chieh Hsieh ,  Ying-Ching Shih ,  Po-Hao Tsai ,  Cheng-Lin Huang ,  Jing-Cheng Lin

IPC分类号： H01L23/00 ,  H01L23/14 ,  H01L25/04 ,  H01L25/00 ,  H01L23/498

CPC分类号： H01L24/11 ,  H01L23/147 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/04 ,  H01L25/50 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05184 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/10145 ,  H01L2224/10156 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11831 ,  H01L2224/13017 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13565 ,  H01L2224/13578 ,  H01L2224/13686 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/3651 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01047 ,  H01L2924/049 ,  H01L2924/053 ,  H01L2924/00

摘要： A package component is free from active devices therein. The package component includes a substrate, a through-via in the substrate, a top dielectric layer over the substrate, and a metal pillar having a top surface over a top surface of the top dielectric layer. The metal pillar is electrically coupled to the through-via. A diffusion barrier is over the top surface of the metal pillar. A solder cap is disposed over the diffusion barrier.

摘要翻译： 封装组件不含其中的有源器件。 封装部件包括衬底，衬底中的通孔，衬底上的顶部电介质层和在顶部电介质层的顶表面上方具有顶表面的金属柱。 金属柱电连接到通孔。 扩散阻挡层在金属支柱的上表面之上。 焊料帽设置在扩散阻挡层上。

公开(公告)号：US09425168B2

公开(公告)日：2016-08-23

申请号：US14256233

申请日：2014-04-18

申请人： WIRE TECHNOLOGY CO., LTD.

发明人： Tung-Han Chuang ,  Hsing-Hua Tsai ,  Jun-Der Lee

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13139 ,  H01L2224/1319 ,  H01L2224/1329 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16503 ,  H01L2224/73204 ,  H01L2224/8109 ,  H01L2224/81203 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/8181 ,  H01L2224/8381 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00015 ,  H01L2924/01004 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/0134 ,  H01L2924/0135 ,  H01L2924/12041 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2924/3651 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/0781 ,  H01L2924/07802 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2924/0103 ,  H01L2924/01029 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01083 ,  H01L2924/00012 ,  H01L2224/11462 ,  H01L2224/13144 ,  H01L2924/1204

摘要： A stud bump structure, a package structure thereof and method of manufacturing the package structure are provided. The stud bump structure include a first chip; and a silver alloy stud bump disposed on the substrate, wherein the on-chip silver alloy stud bump includes Pd of 0.01˜10 wt %, while the balance is Ag. The package structure further includes a substrate having an on-substrate bond pad electrically connected to the on-chip silver alloy stud bump by flip chip bonding.

摘要翻译： 提供了一种螺柱凸块结构，其封装结构和制造封装结构的方法。 螺柱凸块结构包括第一芯片; 和设置在基板上的银合金凸块凸块，其中片上银合金凸块凸块包括0.01〜10重量％的Pd，余量为Ag。 封装结构还包括具有通过倒装芯片接合电连接到片上银合金柱形凸块的衬底上焊盘的衬底。

公开(公告)号：US09412709B2

公开(公告)日：2016-08-09

申请号：US13898949

申请日：2013-05-21

申请人： Sheila F. Chopin ,  Min Ding ,  Varughese Mathew ,  Scott S. Roth

发明人： Sheila F. Chopin ,  Min Ding ,  Varughese Mathew ,  Scott S. Roth

IPC分类号： H01L21/56 ,  H01L21/44 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L24/02 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/0218 ,  H01L2224/0219 ,  H01L2224/03005 ,  H01L2224/03009 ,  H01L2224/03015 ,  H01L2224/03019 ,  H01L2224/034 ,  H01L2224/03622 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05 ,  H01L2224/05565 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/48507 ,  H01L2224/48824 ,  H01L2224/73265 ,  H01L2924/01012 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/365 ,  H01L2924/3651 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

摘要： A packaged semiconductor device is made by forming a conductive pad on an external surface of an integrated circuit device, forming a passivation layer over the conductive pad, removing a portion of the passivation layer over a bond area on the conductive pad, forming a sacrificial anode around a majority of a periphery surrounding the bond area, forming a conductive bond in the bond area, and forming an encapsulating material around the conductive bond and an exposed portion of the sacrificial anode.

摘要翻译： 通过在集成电路器件的外表面上形成导电焊盘来形成封装的半导体器件，在导电焊盘上方形成钝化层，在导电焊盘上的接合区域上去除钝化层的一部分，形成牺牲阳极 在围绕结合区域的周边的大部分周围，在接合区域中形成导电结合，以及在导电接合周围形成封装材料和牺牲阳极的暴露部分。

公开(公告)号：US09376541B2

公开(公告)日：2016-06-28

申请号：US14288997

申请日：2014-05-28

申请人： Samsung Electronics Co., Ltd.

发明人： Un-byoung Kang ,  Kyung-wook Paik ,  Tae-Je Cho ,  Young-kun Jee ,  Sun-kyoung Seo ,  Yong-won Choi ,  Ji-won Shin

IPC分类号： H01L23/29 ,  C08K3/08 ,  H01L25/065 ,  H01L23/00

CPC分类号： C08K3/08 ,  C08K2003/0893 ,  C08K2201/011 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/91 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1134 ,  H01L2224/13111 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16503 ,  H01L2224/17181 ,  H01L2224/2732 ,  H01L2224/27436 ,  H01L2224/2929 ,  H01L2224/29318 ,  H01L2224/32505 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/3651 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/27 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/8211

摘要： A non-conductive material layer, selected from a non-conductive film and a non-conductive polymer paste, and containing a dispersion of zinc (Zn) particles is disclosed, together with semiconductor packages including the non-conductive material layer. The non-conductive material layer contains zinc (Zn) particles having an average particle diameter of about 1 nm to about 200 nm in a non-conductive polymer base material of a film type, and a semiconductor package includes the non-conductive film. By using the non-conductive film and/or the non-conductive paste containing the zinc dispersion, e a semiconductor package having excellent electric connection properties and high reliability may be manufactured through simple processes at low manufacturing costs.

摘要翻译： 公开了一种选自非导电膜和非导电聚合物浆料并含有锌（Zn）颗粒的分散体的非导电材料层以及包括非导电材料层的半导体封装。 非导电材料层在薄膜型非导电性聚合物基材中含有平均粒径为约1nm〜约200nm的锌（Zn）颗粒，半导体封装包括非导电膜。 通过使用含有锌分散体的非导电性膜和/或非导电性糊剂，可以以低制造成本通过简单的工艺制造具有优异的电连接性能和高可靠性的半导体封装。

公开(公告)号：US09024442B2

公开(公告)日：2015-05-05

申请号：US13508864

申请日：2011-08-04

申请人： Shinichi Terashima ,  Masamoto Tanaka ,  Katsuichi Kimura

发明人： Shinichi Terashima ,  Masamoto Tanaka ,  Katsuichi Kimura

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  B23K35/26 ,  C22C13/00 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H05K3/34

CPC分类号： B23K35/262 ,  C22C13/00 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49866 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/11334 ,  H01L2224/13005 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13688 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/3651 ,  H01L2924/37 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2203/041 ,  H01L2224/05644 ,  H01L2224/05164 ,  H01L2224/05155 ,  H01L2224/05147 ,  H01L2924/01083 ,  H01L2924/01028 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01026 ,  H01L2924/2076 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

摘要： The present invention relates to a solder ball for semiconductor packaging and an electronic member having such solder ball. Specifically there are provided: a solder ball capable of ensuring a sufficient thermal fatigue property even when a diameter thereof is not larger than 250 μm as observed in recent years; and an electronic member having such solder ball. More specifically, there are provided: a solder ball for semiconductor packaging that is made of a solder alloy containing Sn as a main element, 0.1-2.5% Ag by mass, 0.1-1.5% Cu by mass and at least one of Mg, Al and Zn in a total amount of 0.0001-0.005% by mass, such solder ball having a surface including a noncrystalline phase that has a thickness of 1-50 nm and contains at least one of Mg, Al and Zn, O and Sn, and an electronic member having such solder ball.

摘要翻译： 本发明涉及一种用于半导体封装的焊球和具有这种焊球的电子部件。 具体地说，提供了一种能够确保近年来观察到的直径不大于250μm时的足够的热疲劳特性的焊球; 以及具有这种焊球的电子部件。 更具体地说，提供一种半导体封装用焊料球，其由以Sn为主要元素的焊料合金制成，质量％为0.1〜2.5质量％，Cu为0.1〜1.5质量％，Mg，Al 和Zn，其总量为0.0001-0.005质量％，这种焊球具有包括厚度为1-50nm并且包含Mg，Al和Zn，O和Sn中的至少一种的非晶相的表面，以及 具有这种焊球的电子部件。

公开(公告)号：US08901735B2

公开(公告)日：2014-12-02

申请号：US14161111

申请日：2014-01-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua Yu ,  Ying Ching Shih ,  Po-Hao Tsai ,  Chin-Fu Kao ,  Cheng-Lin Huang ,  Cheng-Chieh Hsieh ,  Kuo-Ching Hsu ,  Jing-Cheng Lin ,  Shang-Yun Hou ,  Shin-Puu Jeng

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/02 ,  H01L23/00 ,  H01L25/04 ,  H01L25/00 ,  H01L23/14 ,  H01L23/498

CPC分类号： H01L24/11 ,  H01L23/147 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/04 ,  H01L25/50 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05184 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/10145 ,  H01L2224/10156 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11831 ,  H01L2224/13017 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13565 ,  H01L2224/13578 ,  H01L2224/13686 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/3651 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01047 ,  H01L2924/049 ,  H01L2924/053 ,  H01L2924/00

摘要： A device includes a top dielectric layer having a top surface. A metal pillar has a portion over the top surface of the top dielectric layer. A non-wetting layer is formed on a sidewall of the metal pillar, wherein the non-wetting layer is not wettable to the molten solder. A solder region is disposed over and electrically coupled to the metal pillar.

摘要翻译： 一种器件包括具有顶表面的顶部电介质层。 金属柱在顶部介电层的顶表面上具有一部分。 在金属柱的侧壁上形成非润湿层，其中非润湿层不能熔化到熔融焊料上。 焊料区域设置在金属柱上并电耦合到金属柱。

公开(公告)号：US20140346663A1

公开(公告)日：2014-11-27

申请号：US13898949

申请日：2013-05-21

申请人： Sheila F. Chopin ,  Min Ding ,  Varughese Mathew ,  Scott S. Roth

发明人： Sheila F. Chopin ,  Min Ding ,  Varughese Mathew ,  Scott S. Roth

IPC分类号： H01L23/00

CPC分类号： H01L24/02 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/0218 ,  H01L2224/0219 ,  H01L2224/03005 ,  H01L2224/03009 ,  H01L2224/03015 ,  H01L2224/03019 ,  H01L2224/034 ,  H01L2224/03622 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05 ,  H01L2224/05565 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/48507 ,  H01L2224/48824 ,  H01L2224/73265 ,  H01L2924/01012 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/365 ,  H01L2924/3651 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

摘要： A packaged semiconductor device is made by forming a conductive pad on an external surface of an integrated circuit device, forming a passivation layer over the conductive pad, removing a portion of the passivation layer over a bond area on the conductive pad, forming a sacrificial anode around a majority of a periphery surrounding the bond area, forming a conductive bond in the bond area, and forming an encapsulating material around the conductive bond and an exposed portion of the sacrificial anode.

摘要翻译： 通过在集成电路器件的外表面上形成导电焊盘来形成封装的半导体器件，在导电焊盘上方形成钝化层，在导电焊盘上的接合区域上去除钝化层的一部分，形成牺牲阳极 在围绕结合区域的周边的大部分周围，在接合区域中形成导电结合，以及在导电接合周围形成封装材料和牺牲阳极的暴露部分。