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    VARIABLE RESISTANCE MEMORY DEVICES
    1.
    发明申请
    VARIABLE RESISTANCE MEMORY DEVICES 有权

    公开(公告)号：US20210183950A1

    公开(公告)日：2021-06-17

    申请号：US17027992

    申请日：2020-09-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junghyun CHO

    IPC: H01L27/24 ,  H01L23/522 ,  H01L23/532 ,  H01L23/535 ,  H01L45/00

    Abstract: A variable resistance memory device including a substrate; first and second transistors on the substrate; first conductive lines on the transistors, each of the first conductive lines extending in a first direction, and the first conductive lines being spaced apart from each other; first contact plugs directly contacting substrate-facing surfaces of the first conductive lines, the first contact plugs being electrically connected to the first transistors, respectively; second conductive lines on the first conductive lines, each of the second conductive lines extending in the second direction, and the second conductive lines being spaced apart from each other; second contact plugs directly contacting substrate-facing surfaces of the second conductive lines, the second contact plugs being electrically connected to the second transistors, respectively; and memory units between the conductive lines, wherein each of the second contact plugs does not overlap with any of the memory units in the third direction.

    PLASMA PROCESSING SYSTEM
    2.
    发明申请
    PLASMA PROCESSING SYSTEM 有权

    公开(公告)号：US20220230851A1

    公开(公告)日：2022-07-21

    申请号：US17715453

    申请日：2022-04-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaewon JEONG ,  Daebeom LEE ,  Juho LEE ,  Junghyun CHO

    IPC: H01J37/32 ,  H01L21/3065

    Abstract: A plasma processing system includes a radio-frequency (RF) power source unit configured to generate three RF powers; a process chamber to which a process gas supplied and to which the RF powers are applied to generate a plasma; and an impedance matcher between the RF power source unit and the process chamber, the impedance matcher configured to adjust an impedance. The RF power source unit may include a first RF power source connected to a first electrode located in a lower portion of the process chamber to apply a first RF power having a first frequency, a second RF power source connected to the first electrode and to apply a second RF power having a second frequency, and a third RF power source connected to a second electrode located in an upper portion of the process chamber and to apply a third RF power having a third frequency.

    SEMICONDUCTOR PACKAGE
    3.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20210296222A1

    公开(公告)日：2021-09-23

    申请号：US17333615

    申请日：2021-05-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junghyun CHO ,  Youngsik Hur ,  Youngkwan Lee ,  Jongrok Kim

    IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

    Abstract: A method of manufacturing a semiconductor package includes preparing a core substrate having an upper surface and a lower surface, and including a cavity. A passive component is disposed in the cavity. A first insulating layer is formed on the upper surface of the core substrate and in the cavity and encapsulates the passive component. Through-vias are formed that penetrate the core substrate and the first insulating layer, and a first wiring layer is formed on the first insulating layer. The first wiring layer connects the through-vias and the passive component. A connection structure including an insulating member is formed on the first insulating layer and a redistribution layer is formed in the insulating member. The redistribution layer is connected to the first wiring layer. A semiconductor chip is disposed on an upper surface of the connection structure. The semiconductor chip has connection pads connected to the redistribution layer.

    METAL-INSULATOR-METAL (MIM) CAPACITOR AND SEMICONDUCTOR DEVICE
    4.
    发明申请
    METAL-INSULATOR-METAL (MIM) CAPACITOR AND SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20200273946A1

    公开(公告)日：2020-08-27

    申请号：US16661414

    申请日：2019-10-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： SONG YI KIM ,  Junghyun CHO

    IPC: H01L49/02 ,  H01L27/24 ,  H01L23/522 ,  H01L23/528 ,  H01L45/00

    Abstract: A semiconductor device includes a substrate and memory cell arrays arranged on the substrate in a first direction and second direction. The first direction and second direction are parallel to a top surface of the substrate and intersect each other. The memory cell arrays include a plurality of memory cells. A cell dummy pattern on the substrate is arranged between the memory cell arrays in at least one of the first direction and second direction and extends along a side of the memory cell arrays. A cell conductive pattern is included on the substrate. A cell contact plug is configured to connect the cell dummy pattern and the cell conductive pattern. The cell contact plug is arranged between the cell dummy pattern and the cell conductive pattern in a third direction that is perpendicular to the first direction and the second direction.

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