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公开(公告)号:US20240306383A1
公开(公告)日:2024-09-12
申请号:US18504637
申请日:2023-11-08
Applicant: Samsung Electronics Co., Ltd.
Inventor: Ki Joon KIM
IPC: H10B41/27 , G11C5/06 , H01L21/28 , H01L25/065 , H01L29/51 , H10B41/10 , H10B41/35 , H10B41/40 , H10B43/10 , H10B43/27 , H10B43/35 , H10B43/40 , H10B80/00
CPC classification number: H10B41/27 , G11C5/063 , H01L25/0652 , H01L29/40111 , H01L29/516 , H10B41/10 , H10B41/35 , H10B41/40 , H10B43/10 , H10B43/27 , H10B43/35 , H10B43/40 , H10B80/00 , H01L2225/06506
Abstract: A semiconductor memory device having improved characteristics may be provided. The semiconductor memory device includes a cell substrate, a plurality of gate electrodes sequentially stacked on the cell substrate, a semiconductor layer extending in a vertical direction, intersecting an upper side of the cell substrate, and intersecting the plurality of gate electrodes, and a gate dielectric layer including ferroelectrics between each of the gate electrodes and the semiconductor layer, wherein the semiconductor layer includes an n-type channel layer and a p-type channel layer each extending in the vertical direction, and the n-type channel layer includes an oxide 2-dimensional electron gas (2-DEG) layer extending in the vertical direction.
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公开(公告)号:US20150017743A1
公开(公告)日:2015-01-15
申请号:US14498465
申请日:2014-09-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Kilho LEE , Ki Joon KIM , Se Woong PARK
CPC classification number: H01L43/12 , H01L27/10888 , H01L27/222 , H01L27/228 , H01L29/82
Abstract: Memory devices and methods of fabricating the same include a substrate including a cell region and a peripheral circuit region, data storages on the cell region, first bit lines on and coupled to the data storages, first contacts coupled to peripheral transistors on the peripheral circuit region, and second bit lines on and coupled to the first contacts. The second bit lines may each have a lowermost surface lower than a lowermost surface of the data storages.
Abstract translation: 存储器件及其制造方法包括:包括单元区域和外围电路区域的衬底,在单元区域上的数据存储,在数据存储器上并耦合到数据存储器的第一位线,耦合到外围电路区域上的外围晶体管的第一触点 以及在第一触点上并耦合到第一触点的第二位线。 第二位线可以各自具有低于数据存储器的最低表面的最下表面。
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公开(公告)号:US20250169077A1
公开(公告)日:2025-05-22
申请号:US18663210
申请日:2024-05-14
Applicant: Samsung Electronics Co., Ltd.
Inventor: Ki Joon KIM
Abstract: A semiconductor device includes a cell substrate; a mold structure which includes gate electrodes and mold insulating films alternately stacked on the cell substrate; a channel layer that extends in a vertical direction intersecting an upper side of the cell substrate, inside the mold structure; an insertion layer which includes ferroelectrics and surrounds the channel layer; and a dielectric layer which is not interposed between the insertion layer and the gate electrodes, but is interposed between the insertion layer and the mold insulating films, wherein the gate electrodes are in contact with the insertion layer.
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公开(公告)号:US20240290891A1
公开(公告)日:2024-08-29
申请号:US18465550
申请日:2023-09-12
Applicant: Samsung Electronics Co., Ltd.
Inventor: Ki Joon KIM
IPC: H01L29/786 , H01L27/092 , H01L27/12 , H01L29/24 , H01L29/423 , H01L29/49 , H01L29/66 , H01L29/775
CPC classification number: H01L29/78696 , H01L27/092 , H01L27/1207 , H01L29/24 , H01L29/42392 , H01L29/4908 , H01L29/66969 , H01L29/775
Abstract: A semiconductor device including a substrate, a first bridge pattern spaced apart from the substrate and extending in a first direction and including a two-dimensional chalcogenide in which a semiconductor element and a chalcogen element are combined, a gate structure extending in a second direction intersecting the first direction and through which the first bridge pattern penetrates, a gate spacer extending along a side surface of the gate structure and through which the first bridge pattern penetrates and a source/drain pattern connected to the first bridge pattern on a side surface of the gate spacer, wherein the first bridge pattern includes a first chalcogenization portion overlapping the gate structure and a second chalcogenization portion overlapping the gate spacer, and a concentration of the chalcogen element in the second chalcogenization portion is lower than a concentration of the chalcogen element in the first chalcogenization portion, may be provided.
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