公开(公告)号：US08982618B2

公开(公告)日：2015-03-17

申请号：US13795750

申请日：2013-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Hyun Joo ,  Il-Han Park ,  Ki-Whan Song

IPC: G11C16/04 ,  G11C16/34 ,  G11C11/56 ,  G11C16/10

CPC classification number: G11C16/3418 ,  G11C11/5628 ,  G11C16/06 ,  G11C16/10 ,  G11C16/26

Abstract: A nonvolatile memory device comprises a nonvolatile memory chip comprising a static latch, first and second dynamic latches that receive the data stored in the static latch through a floating node, and a memory cell configured to store multi-bit data. The nonvolatile memory device performs a refresh operation on the first dynamic latch where externally supplied first single bit data is stored in the first dynamic latch, performs a refresh operation on the second dynamic latch where externally supplied second single bit data is stored in the second dynamic latch, and programs the memory cell using the data stored in the first and second dynamic latches after the first and second single bit data are stored in the respective first and second dynamic latches.

Abstract translation: 非易失性存储器件包括非易失性存储器芯片，其包括静态锁存器，通过浮动节点接收存储在静态锁存器中的数据的第一和第二动态锁存器以及被配置为存储多位数据的存储器单元。 非易失性存储器件对第一动态锁存器执行刷新操作，其中外部提供的第一单位数据被存储在第一动态锁存器中，对外部提供的第二单位数据存储在第二动态锁存器中的第二动态锁存器执行刷新操作 在第一和第二单个位数据存储在相应的第一和第二动态锁存器中之后，使用存储在第一和第二动态锁存器中的数据对存储器单元进行锁存和编程。

公开(公告)号：US10593408B2

公开(公告)日：2020-03-17

申请号：US16191656

申请日：2018-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： June-Hong Park ,  Ki-Whan Song ,  Bong-Soon Lim ,  Su-Chang Jeon ,  Jin-Young Kim ,  Chang-Yeon Yu ,  Dong-Kyo Shim ,  Seong-Jin Kim

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/24 ,  G11C7/10 ,  G11C16/26 ,  G11C7/12 ,  G11C16/04 ,  G11C16/32

Abstract: A nonvolatile memory device including a memory cell array having a plurality of planes; a plurality of page buffers arranged corresponding to each of the plurality of planes; and a control logic circuit configured to transmit a bit line setup signal to each of the plurality of page buffers. Each of the plurality of page buffers includes a precharge circuit configured to precharge a sensing node and a bit line in response to the bit line setup signal, and a shutoff circuit configured to perform a bit line shutoff operation in response to a bit line shutoff signal. The control logic circuit is configured to control a transition time when a level of the bit line setup signal is changed according to a gradient of the bit line shutoff signal which is changed from a first level to a second level.

公开(公告)号：US10170192B2

公开(公告)日：2019-01-01

申请号：US15717992

申请日：2017-09-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： June-Hong Park ,  Ki-Whan Song ,  Bong-Soon Lim ,  Su-Chang Jeon ,  Jin-Young Kim ,  Chang-Yeon Yu ,  Dong-Kyo Shim ,  Seong-Jin Kim

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24

Abstract: A nonvolatile memory device including a memory cell array having a plurality of planes; a plurality of page buffers arranged corresponding to each of the plurality of planes; and a control logic circuit configured to transmit a bit line setup signal to each of the plurality of page buffers. Each of the plurality of page buffers includes a precharge circuit configured to precharge a sensing node and a bit line in response to the bit line setup signal, and a shutoff circuit configured to perform a bit line shutoff operation in response to a bit line shutoff signal. The control logic circuit is configured to control a transition time when a level of the bit line setup signal is changed according to a gradient of the bit line shutoff signal which is changed from a first level to a second level.