公开(公告)号：US10418548B2

公开(公告)日：2019-09-17

申请号：US16018700

申请日：2018-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shinhee Han ,  Kiseok Suh ,  KyungTae Nam ,  Woojin Kim ,  Kwangil Shin ,  Minkyoung Joo ,  Gwanhyeob Koh

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L27/22 ,  G11C11/16

Abstract: A method of fabricating a magnetic memory device includes forming an interlayered insulating layer on a substrate, forming a landing pad to pass through the interlayered insulating layer, forming a protection insulating layer on the interlayered insulating layer to cover a top surface of the landing pad, forming a bottom electrode to pass through the protection insulating layer and through the interlayered insulating layer, forming a magnetic tunnel junction layer on the protection insulating layer; and patterning the magnetic tunnel junction layer to form a magnetic tunnel junction pattern on the bottom electrode.

公开(公告)号：US20250151627A1

公开(公告)日：2025-05-08

申请号：US18671519

申请日：2024-05-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kilho Lee ,  Yongjae Kim ,  Kiseok Suh

IPC: H10N50/01 ,  H10B61/00 ,  H10N50/10

Abstract: A method of manufacturing a magnetoresistive memory device includes: forming, sequentially, a magnetic tunnel junction (MTJ) structure and a metal layer on a substrate in first and second cell regions; performing a first oxidation process on the metal layer in the first and second cell regions to form a first metal oxide layer; performing an ion implantation process on the first metal oxide layer in the first cell region to form a second metal oxide layer while the first metal oxide layer is exposed in the second cell region; and patterning the MTJ structure, the first and second metal oxide layers to form a first memory element including a first MTJ structure and the second metal oxide layer in the first cell region, and to form a second memory element including a second MTJ structure and the first metal oxide layer in the second cell region.

公开(公告)号：US10032981B2

公开(公告)日：2018-07-24

申请号：US15244344

申请日：2016-08-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shinhee Han ,  Kiseok Suh ,  KyungTae Nam ,  Woojin Kim ,  Kwangil Shin ,  Minkyoung Joo ,  Gwanhyeob Koh

IPC: H01L21/00 ,  H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L27/22 ,  G11C11/16

Abstract: A method of fabricating a magnetic memory device includes forming an interlayered insulating layer on a substrate, forming a landing pad to pass through the interlayered insulating layer, forming a protection insulating layer on the interlayered insulating layer to cover a top surface of the landing pad, forming a bottom electrode to pass through the protection insulating layer and through the interlayered insulating layer, forming a magnetic tunnel junction layer on the protection insulating layer; and patterning the magnetic tunnel junction layer to form a magnetic tunnel junction pattern on the bottom electrode.

公开(公告)号：US09620190B2

公开(公告)日：2017-04-11

申请号：US14609977

申请日：2015-01-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaekyu Lee ,  Kiseok Suh

IPC: G11C11/16 ,  G11C13/00 ,  G11C13/02

CPC classification number: G11C11/165 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0021 ,  G11C13/003 ,  G11C13/025 ,  G11C2213/52 ,  G11C2213/79 ,  G11C2213/82

Abstract: A magnetic memory device can include a plurality of separately controllable magnetic memory segments configured to store data. A plurality of separately controllable source lines can each be coupled to a respective one of the plurality of separately controllable magnetic memory segments.

公开(公告)号：US08901009B2

公开(公告)日：2014-12-02

申请号：US14134008

申请日：2013-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaekyu Lee ,  Kiseok Suh ,  Tae Eung Yoon

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1691 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1641

Abstract: A memory device includes a lower interconnection in a semiconductor substrate, the lower interconnection being made of a material different from the semiconductor substrate, a selection element on the lower interconnection, and a memory element on the selection element.

Abstract translation: 存储器件包括半导体衬底中的下互连，下互连由不同于半导体衬底的材料制成，下互连上的选择元件以及选择元件上的存储元件。