公开(公告)号：US20240429214A1

公开(公告)日：2024-12-26

申请号：US18820569

申请日：2024-08-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il CHOI ,  Gyuho KANG ,  Heewon KIM ,  Sechul PARK ,  Jongho PARK ,  Junyoung PARK

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

Abstract: Disclosed is a semiconductor package comprising an interposer substrate having first and second surfaces opposite each other and including a wiring layer adjacent to the first surface, a semiconductor chip on the first surface of the interposer substrate, a passivation layer on the first surface of the interposer substrate and covering the semiconductor chip, and redistribution patterns in the passivation layer and connected to the semiconductor chip. The semiconductor chip has third and fourth surfaces opposite to each other. The third surface of the semiconductor chip faces the first surface of the interposer substrate. The redistribution patterns are connected to the fourth surface of the semiconductor chip. The semiconductor chip includes chip pads adjacent to the third surface and chip through electrodes connected to the chip pads. Each of the chip pads is directly bonded to a corresponding one of wiring patterns in the wiring layer.

公开(公告)号：US20230060115A1

公开(公告)日：2023-02-23

申请号：US17723552

申请日：2022-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sechul PARK ,  Unbyoung KANG ,  Heewon KIM ,  Jongho PARK ,  Hyojin YUN ,  Juil CHOI

IPC: H01L23/00 ,  H01L25/065

Abstract: A semiconductor package includes a first semiconductor chip on a base chip, a second semiconductor chip on the first semiconductor chip in a first direction, each of the first and second semiconductor chips including a TSV and being electrically connected to each other via the TSV, dam structures on the base chip and surrounding a periphery of the first semiconductor chip, a first adhesive film between the base chip and the first semiconductor chip, a portion of the first adhesive film filling a space between the first semiconductor chip and the dam structures, a second adhesive film between the first semiconductor chip and the second semiconductor chip, a portion of the second adhesive film overlapping the dam structures in the first direction, and an encapsulant encapsulating a portion of each of the dam structures, the first semiconductor chip, and the second semiconductor chip.

公开(公告)号：US20220399316A1

公开(公告)日：2022-12-15

申请号：US17677453

申请日：2022-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il CHOI ,  Gyuho KANG ,  Heewon KIM ,  Sechul PARK ,  Jongho PARK ,  Junyoung PARK

IPC: H01L25/10 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L23/48

Abstract: Disclosed is a semiconductor package comprising an interposer substrate having first and second surfaces opposite each other and including a wiring layer adjacent to the first surface, a semiconductor chip on the first surface of the interposer substrate, a passivation layer on the first surface of the interposer substrate and covering the semiconductor chip, and redistribution patterns in the passivation layer and connected to the semiconductor chip. The semiconductor chip has third and fourth surfaces opposite to each other. The third surface of the semiconductor chip faces the first surface of the interposer substrate. The redistribution patterns are connected to the fourth surface of the semiconductor chip. The semiconductor chip includes chip pads adjacent to the third surface and chip through electrodes connected to the chip pads. Each of the chip pads is directly bonded to a corresponding one of wiring patterns in the wiring layer.

公开(公告)号：US20240105536A1

公开(公告)日：2024-03-28

申请号：US18369474

申请日：2023-09-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokbong PARK ,  Sechul PARK ,  Unbyoung KANG ,  Junhyun AN ,  Hyojin YUN ,  Seunghun CHAE

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L25/10

CPC classification number: H01L23/3107 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2924/15174

Abstract: A semiconductor package includes a first redistribution structure, a first semiconductor chip on the first redistribution structure, a first molding layer on the first redistribution structure, the first molding layer including at least one lower recess in a top surface thereof and being disposed on the first semiconductor chip, connection structures on the first redistribution structure, the connection structures extending in a vertical direction and passing through the first molding layer, a first insulating layer on the first molding layer, and a second redistribution structure including a lower redistribution insulating layer on the first insulating layer, wherein the first insulating layer at least partially fills the at least one lower recess of the first molding layer.