公开(公告)号：US20250120165A1

公开(公告)日：2025-04-10

申请号：US18895887

申请日：2024-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seowoo Nam ,  Heonjong Shin ,  Sanghee Lee

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: In the integrated circuit device and a method of manufacturing the same according to an embodiment, in a structure including a backside power distribution network for a device region having an area reduced based on down-scaling, a contact-merged bridge is formed on a source/drain contact, and thus, difficulty of a manufacturing process may be reduced and electrical characteristics may be enhanced.

公开(公告)号：US20240258239A1

公开(公告)日：2024-08-01

申请号：US18427795

申请日：2024-01-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANGBONG LEE ,  Seowoo Nam ,  SUNGHO SEO ,  SEOKMYEONG KANG ,  KyuHoon Choi ,  SEUNGSEOK HA

IPC: H01L23/535 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76832 ,  H01L21/76895

Abstract: A semiconductor device includes: a first interlayer insulating layer disposed on a substrate; a first conductive line disposed in the first interlayer insulating layer and having a protrusion protruding above an upper side of the first interlayer insulating layer; an etch stop layer disposed on the first interlayer insulating layer and the first conductive line; and a via passing through the etch stop layer and contacting the first conductive line, wherein the etch stop layer includes a first etch stop layer having a curved shape in a cross-sectional view and a second etch stop layer disposed on the first etch stop layer and having a thickness variation.

公开(公告)号：US20240153815A1

公开(公告)日：2024-05-09

申请号：US18456561

申请日：2023-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyuhoon Choi ,  Seungseok Ha ,  Seokmyeong Kang ,  Seowoo Nam

IPC: H01L21/768 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/321

CPC classification number: H01L21/76819 ,  H01L21/31053 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/7684

Abstract: A method of manufacturing a semiconductor device includes forming conductive patterns on which stopper layers are formed, respectively, on a substrate including a first region having a first pattern density and a second region having a second pattern density lower than the first pattern density, forming a first interlayer insulating layer on the conductive patterns, exposing at least a portion of the first interlayer insulating layer on the first region and forming a photoresist pattern on the second region, etching at least a portion of the first interlayer insulating layer on the first region, performing first polishing to expose upper surfaces of ones of the stopper layers on the first region, etching the ones of the stopper layers on the first region, forming a second interlayer insulating layer on the conductive patterns, and performing second polishing to expose upper surfaces of ones of the conductive patterns on the first region.

公开(公告)号：US11978668B2

公开(公告)日：2024-05-07

申请号：US17546470

申请日：2021-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ming He ,  Harsono Simka ,  Anthony Dongick Lee ,  Seowoo Nam ,  Sang Hoon Ahn

IPC: H01L21/768 ,  H01L21/3105 ,  H01L21/311 ,  H01L23/532 ,  H01L23/535

CPC classification number: H01L21/76895 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76805 ,  H01L21/76819 ,  H01L21/76829 ,  H01L23/53242 ,  H01L23/53257 ,  H01L23/535

Abstract: Integrated circuit devices including a via and methods of forming the same are provided. The methods may include forming a conductive wire structure on a substrate. The conductive wire structure may include a first insulating layer and a conductive wire stack in the first insulating layer, and the conductive wire stack may include a conductive wire and a mask layer stacked on the substrate. The method may also include forming a recess in the first insulating layer by removing the mask layer, the recess exposing the conductive wire, forming an etch stop layer and then a second insulating layer on the first insulating layer and in the recess of the first insulating layer, and forming a conductive via extending through the second insulating layer and the etch stop layer and contacting the conductive wire.