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    System on chip
    2.
    发明授权
    System on chip 有权

    公开(公告)号：US11201150B2

    公开(公告)日：2021-12-14

    申请号：US16746071

    申请日：2020-01-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Hoon Baek ,  Sun-Young Park ,  Sang-Kyu Oh ,  Ha-young Kim ,  Jung-Ho Do ,  Moo-Gyu Bae ,  Seung-Young Lee

    IPC: H01L23/48 ,  H01L29/40 ,  H01L27/088 ,  H01L27/02 ,  H01L27/11 ,  H01L21/84 ,  H01L27/12 ,  H01L21/8234 ,  H01L23/528

    Abstract: A system on chip includes first to third nanowires extending in a second direction, first to third gate lines respectively surrounding the first to third nanowires, each of the first to third gate lines extending in a first direction across the second direction, a gate isolation region cutting the first to third gate lines and extending in the second direction, a first gate contact formed on the second gate line arranged between the first gate line and the third gate line, and electrically connecting the cut second gate line, a second gate contact formed on the first gate line, a third gate contact formed on the third gate line, a first metal line electrically connecting the second gate contact and the third gate contact; and a second metal line electrically connected to the first gate contact.

    System on chip
    3.
    发明授权
    System on chip 有权

    公开(公告)号：US10050032B2

    公开(公告)日：2018-08-14

    申请号：US15416016

    申请日：2017-01-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Hoon Baek ,  Sun-Young Park ,  Sang-Kyu Oh ,  Ha-Young Kim ,  Jung-Ho Do ,  Moo-Gyu Bae ,  Seung-Young Lee

    IPC: H01L23/48 ,  H01L29/40 ,  H01L27/088 ,  H01L23/528 ,  H01L27/02 ,  H01L27/11 ,  H01L21/8234

    Abstract: Systems on chips are provided. A system on chip (SoC) includes a first gate line, a second gate line and a third gate line extending in a first direction, a gate isolation region cutting the first gate line, the second gate line and the third gate line and extending in a second direction across the first direction, a first gate contact formed on the second gate line arranged between the first gate line and the third gate line, and electrically connecting the cut second gate line, a second gate contact formed on the first gate line, a third gate contact formed on the third gate line, a first metal line electrically connecting the second gate contact and the third gate contact, and a second metal line electrically connected to the first gate contact.

    System on chip
    4.
    发明授权
    System on chip 有权

    公开(公告)号：US10541237B2

    公开(公告)日：2020-01-21

    申请号：US16037581

    申请日：2018-07-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Hoon Baek ,  Sun-Young Park ,  Sang-Kyu Oh ,  Ha-Young Kim ,  Jung-Ho Do ,  Moo-Gyu Bae ,  Seung-Young Lee

    IPC: H01L23/48 ,  H01L29/40 ,  H01L27/088 ,  H01L27/02 ,  H01L27/11 ,  H01L21/8234 ,  H01L23/528

    Abstract: A method is provided. The method includes forming a first to third gate lines on a substrate, the second gate line formed between the first and third gate lines; forming a gate isolation region to cut the first to third gate lines into two first sub gate lines, two second sub gate lines and two third sub gate lines, respectively; forming a first gate contact on one of the two first sub gate lines; forming a second gate contact on the two second sub gate lines; forming a third gate contact on one of the two third sub gate lines; forming a first metal line to connect the first and third gate contacts; and forming a second metal line. The first to third gate lines extend in a first direction, and the gate isolation region extends in a second direction different from the first direction.

    Semiconductor devices
    6.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US11183497B2

    公开(公告)日：2021-11-23

    申请号：US16531327

    申请日：2019-08-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae-Boong Lee ,  Jae-Ho Park ,  Sang-Hoon Baek ,  Ji-Su Yu ,  Seung-Young Lee ,  Jong-Hoon Jung

    IPC: H01L27/092 ,  H01L29/06 ,  H01L27/02

    Abstract: A semiconductor device includes first group active fins and a first diffusion prevention pattern. The first group active fins are spaced apart from each other in a second direction, and each of the first group active fins extends in a first direction different from the second direction on a first region of a substrate including the first region and a second region. The first diffusion prevention pattern extends on the first region of the substrate in the second direction through the first group active fins. The first group active fins include first and second active fins. The first diffusion prevention pattern extends through a central portion of the first active fin in the first direction to divide the first active fin, and extends through and contacts an end of the second active fin in the first direction.

    Method and system for designing semiconductor device
    7.
    发明授权
    Method and system for designing semiconductor device 有权

    公开(公告)号：US09842182B2

    公开(公告)日：2017-12-12

    申请号：US14845556

    申请日：2015-09-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Hoon Baek ,  Tae-Joong Song ,  Gi-Young Yang ,  Jeong-Ho Do

    IPC: G06F17/50 ,  H01L29/66

    CPC classification number: G06F17/5072 ,  G06F17/5081 ,  H01L29/6681

    Abstract: A method of designing a semiconductor device and system for designing a semiconductor device are provided. The method of designing a semiconductor device includes providing a standard cell layout which includes an active region and a dummy region; determining a first fin pitch between a first active fin and a second active fin in the active region and a second fin pitch between a first dummy fin and a second dummy fin in the dummy region; placing the first and second active fins in the active region and the first and second dummy fins in the dummy region using the first and second fin pitches; and verifying the standard cell layout.

    System on chip
    8.
    发明授权
    System on chip 有权
    片上系统

    公开(公告)号：US09589955B2

    公开(公告)日：2017-03-07

    申请号：US14872774

    申请日：2015-10-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Hoon Baek ,  Sun-Young Park ,  Sang-Kyu Oh ,  Ha-Young Kim ,  Jung-Ho Do ,  Moo-Gyu Bae ,  Seung-Young Lee

    IPC: H01L23/48 ,  H01L29/40 ,  H01L27/088 ,  H01L27/02 ,  H01L27/11

    CPC classification number: H01L27/088 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/1104

    Abstract: Systems on chips are provided. A system on chip (SoC) includes a first gate line, a second gate line and a third gate line extending in a first direction, a gate isolation region cutting the first gate line, the second gate line and the third gate line and extending in a second direction across the first direction, a first gate contact formed on the second gate line arranged between the first gate line and the third gate line, and electrically connecting the cut second gate line, a second gate contact formed on the first gate line, a third gate contact formed on the third gate line, a first metal line electrically connecting the second gate contact and the third gate contact, and a second metal line electrically connected to the first gate contact.

    Abstract translation: 提供芯片系统。 片上系统（SoC）包括第一栅极线，第二栅极线和沿第一方向延伸的第三栅极线，栅极隔离区域切割第一栅极线，第二栅极线和第三栅极线并且在 在第一方向上的第二方向，形成在第二栅极线上的第一栅极接触，布置在第一栅极线和第三栅极线之间，并且电连接切割的第二栅极线，形成在第一栅极线上的第二栅极接触， 形成在第三栅极线上的第三栅极触点，电连接第二栅极触点和第三栅极触点的第一金属线以及电连接到第一栅极触点的第二金属线。

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    10.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20150137262A1

    公开(公告)日：2015-05-21

    申请号：US14465968

    申请日：2014-08-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kang-Hyun Baek ,  Sung-Hyun Park ,  Sang-Hoon Baek ,  Tae-Joong Song

    IPC: H01L29/78 ,  H01L27/11

    CPC classification number: H01L29/785 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1211 ,  H01L29/0696 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/66818

    Abstract: A semiconductor device includes: active fins protruding from an active layer and extending in a first direction; a gate structure on the active fins extending in a second direction intersecting the first direction; and a spacer on at least one side of the gate structure, wherein each of the active fins includes a first region and a second region adjacent to the first direction in the first direction, and a width of the first region in the second direction is different from a width of the second region in the second direction.

    Abstract translation: 半导体器件包括：从有源层突出并沿第一方向延伸的有源鳍; 主动翅片上的栅极结构沿与第一方向相交的第二方向延伸; 以及在所述栅极结构的至少一侧上的间隔物，其中所述活性鳍片中的每一个包括第一区域和与所述第一方向上的所述第一方向相邻的第二区域，并且所述第一区域在所述第二方向上的宽度不同 从第二方向的第二区域的宽度。

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