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公开(公告)号：US20230024858A1
公开(公告)日：2023-01-26
申请号：US17834074
申请日：2022-06-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Unghwan Pi
Abstract: A processing apparatus includes a bit-cell array including at least one bit-cell line including a plurality of bit-cells electrically connected to each other in series, wherein each of the plurality of bit-cells includes: a first magnetic resistor that is configured to store a first resistance value based on a movement of a location of a magnetic domain-wall; a second magnetic resistor that is configured to store a second resistance value, wherein the second resistance value is equal to or less than the first resistance value; a first switching element configured to switch an electrical signal applied to the first magnetic resistor; and a second switching element configured to switch an electrical signal applied to the second magnetic resistor.
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公开(公告)号：US20250040443A1
公开(公告)日：2025-01-30
申请号：US18776690
申请日：2024-07-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Unghwan Pi , Stuart Papworth Parkin , Jaechun Jeon , Jaekeun Kim , Andrea Migliorini
Abstract: According to a method of manufacturing a magnetic memory device, various types of magnetic memory devices can be manufactured at low cost by manufacturing a plurality of magnetic modules by using a delamination phenomenon of pattern segments and stacking the plurality of magnetic modules to complete a stacked memory device.
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Patent Agency Ranking
公开(公告)号：US20250029670A1
公开(公告)日：2025-01-23
申请号：US18774226
申请日：2024-07-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Unghwan Pi , Stuart Papworth Parkin , Andrea Migliorini , Jaechun Jeon
Abstract: A method of operating a magnetic memory device includes: (i) applying a first current to a free layer of a magnetic tunnel junction structure, which includes a magnetic translation unit (MTU) extending between a first magnetic pad and a second magnetic pad, and a tunnel barrier layer and a pinned layer stacked on the MTU, so that a multi-domain is established within the MTU, (ii) applying a magnetic field to the free layer so that the magnetization direction of the MTU switches to become anti-parallel to the magnetization directions of the first magnetic pad and the second magnetic pad, (iii) applying a second current to the free layer so that a portion of the multi-domain penetrates into the first magnetic pad, and (iv) applying another magnetic field to the free layer so that the magnetization direction of the first magnetic pad switches.
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公开(公告)号：US11942131B2
公开(公告)日：2024-03-26
申请号：US17834074
申请日：2022-06-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Unghwan Pi
CPC classification number: G11C11/1673 , G11C11/1655 , G11C11/1675 , G11C11/1697 , G11C11/54
Abstract: A processing apparatus includes a bit-cell array including at least one bit-cell line including a plurality of bit-cells electrically connected to each other in series, wherein each of the plurality of bit-cells includes: a first magnetic resistor that is configured to store a first resistance value based on a movement of a location of a magnetic domain-wall; a second magnetic resistor that is configured to store a second resistance value, wherein the second resistance value is equal to or less than the first resistance value; a first switching element configured to switch an electrical signal applied to the first magnetic resistor; and a second switching element configured to switch an electrical signal applied to the second magnetic resistor.
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公开(公告)号：US11227665B2
公开(公告)日：2022-01-18
申请号：US17001740
申请日：2020-08-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Eunsun Noh , Sungchul Lee , Unghwan Pi
Abstract: A magnetic memory device includes a reading unit on a substrate, a magnetic track layer on the reading unit, the magnetic track layer including a bottom portion between first and second sidewall portions, and a mold structure on the bottom portion of the magnetic track layer, and between the first and second sidewall portions. The mold structure includes first and second mold layers alternately arranged in a first direction perpendicular to a top surface of the substrate, and the magnetic track layer includes magnetic domains and magnetic domain walls between magnetic domains, the first and second sidewall portions of the magnetic track layer including sidewall notches corresponding to the magnetic domain walls, and the bottom portion includes a bottom notch corresponding to one of the magnetic domain walls.
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公开(公告)号：US20250029644A1
公开(公告)日：2025-01-23
申请号：US18773949
申请日：2024-07-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Unghwan Pi , Stuart Papworth Parkin , Jaechun Jeon , Jaekeun Kim , Andrea Migliorini
Abstract: A magnetic memory device includes a lower magnetic track layer extending in a first direction and including a plurality of first magnetic domains, a spacer layer on the lower magnetic track layer and extending in the first direction, an upper magnetic track layer on the spacer layer and extending in the first direction, the upper magnetic track layer including a plurality of second magnetic domains, and a plurality of read units on the upper magnetic track layer and arranged apart from one another in the first direction, wherein the plurality of first magnetic domains and the plurality of second magnetic domains have magnetization directions parallel to each other at positions overlapping each other in a second direction perpendicular to the first direction.
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公开(公告)号：US11557720B2
公开(公告)日：2023-01-17
申请号：US17110524
申请日：2020-12-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyunghwan Lee , Yongseok Kim , Kohji Kanamori , Unghwan Pi , Hyuncheol Kim , Sungwon Yoo , Jaeho Hong
Abstract: A memory device includes a magnetic track layer extending on a substrate, the magnetic track layer having a folded structure that is two-dimensionally villi-shaped, a plurality of reading units including a plurality of fixed layers and a tunnel barrier layer between the magnetic track layer and each of the plurality of fixed layers, and a plurality of bit lines extending on different ones of the plurality of reading units, the plurality of reading units being between the magnetic track layer and corresponding ones of the plurality of bit lines.
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