公开(公告)号：US20220415772A1

公开(公告)日：2022-12-29

申请号：US17673865

申请日：2022-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yanggyoo Jung ,  Seungbin Baek ,  Hyunjung Song ,  Sangmin Yong

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L23/00

Abstract: Provided is a semiconductor package including a first wiring pad on a package substrate; a first wiring connection part on the first wiring pad and including a wiring solder layer; a second wiring pad on the package substrate; a second wiring connection part on the second wiring pad and including a conductor; an interposer substrate on the first wiring connection part and the second wiring connection part, wherein a first substrate connection part and a second substrate connection part respectively electrically connected to the first wiring connection part and the second wiring connection part are arranged on a rear surface of the interposer substrate; and semiconductor chips apart from each other in a two-dimensional manner on the interposer substrate, wherein each of the semiconductor chips is electrically connected to the interposer substrate via a chip connection pillar.

公开(公告)号：US11145637B2

公开(公告)日：2021-10-12

申请号：US16583051

申请日：2019-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yanggyoo Jung ,  Chulwoo Kim ,  Hyo-Chang Ryu ,  Yun Seok Choi

IPC: H01L25/16 ,  H01L23/528 ,  H01L23/48 ,  H01L23/367 ,  H01L23/00 ,  H01L21/78 ,  H01L23/498 ,  H01L21/683 ,  H01L21/48 ,  H01L25/00 ,  H01L23/538

Abstract: A semiconductor package may include a package substrate, a first interposer substrate mounted on the package substrate, and a first semiconductor chip disposed on the first interposer substrate. The first interposer substrate may include a first base layer, a second base layer disposed on the first base layer, circuit patterns provided in each of the first base layer and the second base layer, and an integrated device embedded in the first base layer and connected to at least one of the circuit patterns. A top surface of the first base layer may contact a bottom surface of the second base layer.

公开(公告)号：US20240021577A1

公开(公告)日：2024-01-18

申请号：US18121374

申请日：2023-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yanggyoo Jung ,  Seokgeun Ahn ,  Younglyong Kim

IPC: H01L25/065 ,  H10B80/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H10B80/00 ,  H01L23/3135 ,  H01L23/49827 ,  H01L23/5386 ,  H01L23/49816 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/08112 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2924/1431 ,  H01L2924/1437 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/182

Abstract: In some embodiments, a semiconductor package includes a package substrate, a plurality of semiconductor chips on the package substrate, a plurality of interposers between the package substrate and the plurality of semiconductor chips, and a molding layer in contact with the plurality of semiconductor chips and the plurality of interposers. The plurality of semiconductor chips includes a first semiconductor chip, and a second and a third semiconductor chip spaced apart from the first semiconductor chip in horizontal directions. The plurality of interposers includes a first vertical connection interposer vertically overlapping the first semiconductor chip, a second vertical connection interposer vertically overlapping the second semiconductor chip, a first horizontal connection interposer vertically overlapping the first and the second semiconductor chips, and a second horizontal connection interposer vertically overlapping the second and the third semiconductor chips.

公开(公告)号：US11721679B2

公开(公告)日：2023-08-08

申请号：US17396308

申请日：2021-08-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yanggyoo Jung ,  Chulwoo Kim ,  Hyo-Chang Ryu ,  Yun Seok Choi

IPC: H01L25/16 ,  H01L23/528 ,  H01L23/48 ,  H01L23/367 ,  H01L23/00 ,  H01L21/78 ,  H01L23/498 ,  H01L21/683 ,  H01L21/48 ,  H01L25/00 ,  H01L23/538

CPC classification number: H01L25/16 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/528 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/97 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/81005 ,  H01L2224/95001

Abstract: A semiconductor package may include a package substrate, a first interposer substrate mounted on the package substrate, and a first semiconductor chip disposed on the first interposer substrate. The first interposer substrate may include a first base layer, a second base layer disposed on the first base layer, circuit patterns provided in each of the first base layer and the second base layer, and an integrated device embedded in the first base layer and connected to at least one of the circuit patterns. A top surface of the first base layer may contact a bottom surface of the second base layer.

公开(公告)号：US11935867B2

公开(公告)日：2024-03-19

申请号：US17398406

申请日：2021-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yanggyoo Jung ,  Sungeun Kim ,  Sangmin Yong ,  Hae-Jung Yu

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L23/64

CPC classification number: H01L25/0652 ,  H01L23/5383 ,  H01L23/642 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/3511

Abstract: A semiconductor package comprising a package substrate that extends in a first direction and a second direction perpendicular to the first direction, a plurality of logic dies and a memory stack structure on the package substrate, and an interposer substrate mounted in the package substrate. The memory stack structure vertically overlaps the interposer substrate. Each of the logic dies includes a first part that is horizontally offset from the interposer substrate and a second part that vertically overlaps the interposer substrate. The interposer substrate includes an interlayer dielectric layer and a plurality of wiring lines in the interlayer dielectric layer. The memory stack structure is electrically connected to at least one of the logic dies through the wiring lines of the interposer substrate.

公开(公告)号：US20220013475A1

公开(公告)日：2022-01-13

申请号：US17171475

申请日：2021-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chulwoo Kim ,  Yanggyoo Jung ,  Soohyun Nam

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/16 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498

Abstract: A semiconductor package includes a substrate including a wiring, a semiconductor chip structure on the substrate, and electrically connected to the wiring, an underfill resin in a space between the substrate and the semiconductor chip structure, and a stiffener surrounding the semiconductor chip structure, on the substrate, wherein the stiffener includes a conductive frame having a cavity and an insulating filler in the cavity.

公开(公告)号：US12057408B2

公开(公告)日：2024-08-06

申请号：US17171475

申请日：2021-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chulwoo Kim ,  Yanggyoo Jung ,  Soohyun Nam

IPC: H01L23/00 ,  H01L23/16 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L23/16 ,  H01L23/3185 ,  H01L23/3675 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/0652 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/18161 ,  H01L2924/3511

Abstract: A semiconductor package includes a substrate including a wiring, a semiconductor chip structure on the substrate, and electrically connected to the wiring, an underfill resin in a space between the substrate and the semiconductor chip structure, and a stiffener surrounding the semiconductor chip structure, on the substrate, wherein the stiffener includes a conductive frame having a cavity and an insulating filler in the cavity.

公开(公告)号：US12021032B2

公开(公告)日：2024-06-25

申请号：US18326325

申请日：2023-05-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yanggyoo Jung ,  Jinhyun Kang ,  Sungeun Kim ,  Sangmin Yong ,  Seungkwan Ryu

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/5383 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/73 ,  H01L25/0655 ,  H01L24/32 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1517

Abstract: A semiconductor package includes a package substrate. An interposer is disposed on the package substrate. The interposer includes a semiconductor substrate, a wiring layer disposed on an upper surface of the semiconductor substrate and having a plurality of wirings therein, redistribution wiring pads disposed on the wiring layer and electrically connected to the wirings, bonding pads disposed on the redistribution wiring pads, and an insulation layer pattern disposed on the wiring layer and exposing at least a portion of the bonding pad, and first and second semiconductor devices disposed on the interposer. The first and second semiconductor devices are spaced apart from each other and are electrically connected to each other by at least one of the wirings.

公开(公告)号：US20240079349A1

公开(公告)日：2024-03-07

申请号：US18334578

申请日：2023-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yanggyoo Jung ,  Younglyong Kim ,  Seungbin Baek

IPC: H01L23/00 ,  H01L23/053 ,  H01L23/36 ,  H01L23/538 ,  H01L25/065 ,  H01L25/16

CPC classification number: H01L23/562 ,  H01L23/053 ,  H01L23/36 ,  H01L23/5385 ,  H01L24/32 ,  H01L25/0655 ,  H01L25/16 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204

Abstract: A semiconductor package is provided to include a package substrate, a plurality of semiconductor chips mounted on the package substrate, an interposer arranged between the package substrate and the plurality of semiconductor chips, a plurality of passive elements mounted on the package substrate and spaced apart from the interposer, a first stiffener positioned on the package substrate and including a first hole accommodating the interposer and a second hole accommodating the plurality of passive elements, and a second stiffener positioned on the first stiffener and including a third hole communicating with the first hole. The first stiffener has a first coefficient of thermal expansion, and the second stiffener has a second coefficient of thermal expansion different from the first coefficient of thermal expansion.

公开(公告)号：US20240063129A1

公开(公告)日：2024-02-22

申请号：US18299927

申请日：2023-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Geun Ahn ,  Seokhyun Lee ,  Yanggyoo Jung ,  Hwanyoung Choi

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H10B80/00

CPC classification number: H01L23/5383 ,  H01L23/5385 ,  H01L23/49816 ,  H01L24/16 ,  H01L23/3157 ,  H01L23/5384 ,  H10B80/00 ,  H01L2224/16227

Abstract: A semiconductor package includes a package substrate, an interposer substrate on the package substrate, first connection bumps between the package substrate and the interposer substrate, first and second semiconductor chips on the interposer substrate, second connection bumps between the interposer substrate and the first and second semiconductor chips, and an upper molding layer on the interposer substrate and at least partially surrounding the first semiconductor chip and the second semiconductor chip. The interposer substrate includes a plurality of sub-interposers horizontally spaced apart from each other and each including through electrodes, a lower molding layer in a space between the sub-interposers, and a redistribution layer electrically connected to the through electrodes on the sub-interposers and the lower molding layer. A sum of areas of the sub-interposers is less than a sum of areas of the first and second semiconductor chips.