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1.发明授权公开(公告)号：US11145637B2
公开(公告)日：2021-10-12
申请号：US16583051
申请日：2019-09-25
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yanggyoo Jung , Chulwoo Kim , Hyo-Chang Ryu , Yun Seok Choi
IPC: H01L25/16 , H01L23/528 , H01L23/48 , H01L23/367 , H01L23/00 , H01L21/78 , H01L23/498 , H01L21/683 , H01L21/48 , H01L25/00 , H01L23/538
Abstract: A semiconductor package may include a package substrate, a first interposer substrate mounted on the package substrate, and a first semiconductor chip disposed on the first interposer substrate. The first interposer substrate may include a first base layer, a second base layer disposed on the first base layer, circuit patterns provided in each of the first base layer and the second base layer, and an integrated device embedded in the first base layer and connected to at least one of the circuit patterns. A top surface of the first base layer may contact a bottom surface of the second base layer.
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公开(公告)号：US12278222B2
公开(公告)日：2025-04-15
申请号：US18338372
申请日：2023-06-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yanggyoo Jung , Chulwoo Kim , Hyo-Chang Ryu , Yun Seok Choi
IPC: H01L25/16 , H01L21/48 , H01L21/683 , H01L21/78 , H01L23/00 , H01L23/367 , H01L23/48 , H01L23/498 , H01L23/528 , H01L23/538 , H01L25/00
Abstract: A semiconductor package may include a package substrate, a first interposer substrate mounted on the package substrate, and a first semiconductor chip disposed on the first interposer substrate. The first interposer substrate may include a first base layer, a second base layer disposed on the first base layer, circuit patterns provided in each of the first base layer and the second base layer, and an integrated device embedded in the first base layer and connected to at least one of the circuit patterns. A top surface of the first base layer may contact a bottom surface of the second base layer.
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公开(公告)号：US10431522B2
公开(公告)日：2019-10-01
申请号：US15856800
申请日：2017-12-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Min-Ok Na , Jongkook Kim , Hyo-Chang Ryu , Jin-woo Park , BongJin Son , Jangwoo Lee
IPC: H01L23/373 , H01L23/367 , H01L21/56 , H01L25/10 , H01L25/00 , H01L25/065 , H01L23/498 , H01L23/50 , H01L23/00
Abstract: Provided are a thermal interface material layer and a package-on-package device including the same. The package-on-package device may include a thermal interface material layer interposed between lower and upper semiconductor packages and configured to have a specific physical property. Accordingly, it is possible to prevent a crack from occurring in a lower semiconductor chip, when a solder ball joint process is performed to mount the upper semiconductor package on the lower semiconductor package.
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公开(公告)号：US20200006188A1
公开(公告)日：2020-01-02
申请号：US16566380
申请日：2019-09-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Min-Ok Na , Jongkook Kim , Hyo-Chang Ryu , Jin-woo Park , BongJin Son , Jangwoo Lee
IPC: H01L23/373 , H01L23/367 , H01L21/56 , H01L25/10 , H01L25/00 , H01L25/065
Abstract: Provided are a thermal interface material layer and a package-on-package device including the same. The package-on-package device may include a thermal interface material layer interposed between lower and upper semiconductor packages and configured to have a specific physical property. Accordingly, it is possible to prevent a crack from occurring in a lower semiconductor chip, when a solder ball joint process is performed to mount the upper semiconductor package on the lower semiconductor package.
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公开(公告)号：US11721679B2
公开(公告)日：2023-08-08
申请号：US17396308
申请日：2021-08-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yanggyoo Jung , Chulwoo Kim , Hyo-Chang Ryu , Yun Seok Choi
IPC: H01L25/16 , H01L23/528 , H01L23/48 , H01L23/367 , H01L23/00 , H01L21/78 , H01L23/498 , H01L21/683 , H01L21/48 , H01L25/00 , H01L23/538
CPC classification number: H01L25/16 , H01L21/486 , H01L21/4853 , H01L21/6835 , H01L21/78 , H01L23/3675 , H01L23/481 , H01L23/49816 , H01L23/528 , H01L23/5386 , H01L24/16 , H01L24/17 , H01L24/81 , H01L24/97 , H01L25/50 , H01L2221/68372 , H01L2224/16145 , H01L2224/16146 , H01L2224/1703 , H01L2224/17181 , H01L2224/81005 , H01L2224/95001
Abstract: A semiconductor package may include a package substrate, a first interposer substrate mounted on the package substrate, and a first semiconductor chip disposed on the first interposer substrate. The first interposer substrate may include a first base layer, a second base layer disposed on the first base layer, circuit patterns provided in each of the first base layer and the second base layer, and an integrated device embedded in the first base layer and connected to at least one of the circuit patterns. A top surface of the first base layer may contact a bottom surface of the second base layer.
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Patent Agency Ranking
公开(公告)号：US11670565B2
公开(公告)日：2023-06-06
申请号：US17307181
申请日：2021-05-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyo-Chang Ryu , Chulwoo Kim , Juhyun Lyu , Sanghyun Lee , Yun Seok Choi
IPC: H01L23/367 , H01L25/065 , H01L23/00 , H01L25/00
CPC classification number: H01L23/3675 , H01L24/32 , H01L25/0655 , H01L23/367 , H01L25/50 , H01L2224/32237 , H01L2924/3511
Abstract: A semiconductor package includes a first substrate, a first chip structure and a second chip structure spaced apart from each other on the first substrate, a gap region being defined between the first and second chip structures, and a heat dissipation member covering the first chip structure, the second chip structure, and the first substrate, the heat dissipation member including a first trench in an inner top surface of the heat dissipation member, wherein the first trench vertically overlaps with the gap region and has a width greater than a width of the gap region, and wherein the first trench vertically overlaps with at least a portion of a top surface of the first chip structure or a portion of a top surface of the second chip structure.
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公开(公告)号：US08829686B2
公开(公告)日：2014-09-09
申请号：US13678205
申请日：2012-11-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ji-Sun Hong , Young-Min Kim , Jung-Woo Kim , Min-Ok Na , Hyo-Chang Ryu , Jong-Bo Shim
CPC classification number: H01L23/498 , H01L23/3128 , H01L23/49816 , H01L24/73 , H01L25/105 , H01L2224/16145 , H01L2224/16225 , H01L2224/32225 , H01L2224/45139 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2225/1023 , H01L2225/1058 , H01L2924/15311 , H01L2924/15321 , H01L2924/1815 , H01L2924/18161 , H01L2924/00012 , H01L2924/00 , H01L2924/00014
Abstract: A package-on-package assembly includes first and second packages and an adhesion member positioned between the first and second packages and adhering the first and second packages to one another. The first package may include a first substrate having a first surface and a second surface facing each other and including a land pad formed on the first surface, a first semiconductor chip formed on the first surface, and a first encapsulant member encapsulating the first surface and the first semiconductor chip and including a through-via spaced apart from the first semiconductor chip and exposing the land pad and a trench formed between the first semiconductor chip and the through-via, and wherein at least a portion of the trench is filled with adhesion member material.
Abstract translation: 包装包装组件包括第一和第二包装以及定位在第一和第二包装之间并将第一和第二包装彼此粘合的粘合部件。 第一封装可以包括具有第一表面和第二表面的第一衬底，第一表面和第二表面彼此面对并且包括形成在第一表面上的焊盘焊盘，形成在第一表面上的第一半导体芯片和封装第一表面的第一密封剂构件， 所述第一半导体芯片并且包括与所述第一半导体芯片间隔开的通孔，并且暴露所述焊盘焊盘和形成在所述第一半导体芯片和所述通孔之间的沟槽，并且其中所述沟槽的至少一部分填充有粘附 会员资料
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公开(公告)号：US20130187288A1
公开(公告)日：2013-07-25
申请号：US13678205
申请日：2012-11-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ji-Sun Hong , Young-Min Kim , Jung-Woo Kim , Min-Ok Na , Hyo-Chang Ryu , Jong-Bo Shim
IPC: H01L23/498
CPC classification number: H01L23/498 , H01L23/3128 , H01L23/49816 , H01L24/73 , H01L25/105 , H01L2224/16145 , H01L2224/16225 , H01L2224/32225 , H01L2224/45139 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2225/1023 , H01L2225/1058 , H01L2924/15311 , H01L2924/15321 , H01L2924/1815 , H01L2924/18161 , H01L2924/00012 , H01L2924/00 , H01L2924/00014
Abstract: A package-on-package assembly includes first and second packages and an adhesion member positioned between the first and second packages and adhering the first and second packages to one another. The first package may include a first substrate having a first surface and a second surface facing each other and including a land pad formed on the first surface, a first semiconductor chip formed on the first surface, and a first encapsulant member encapsulating the first surface and the first semiconductor chip and including a through-via spaced apart from the first semiconductor chip and exposing the land pad and a trench formed between the first semiconductor chip and the through-via, and wherein at least a portion of the trench is filled with adhesion member material.
Abstract translation: 包装包装组件包括第一和第二包装以及定位在第一和第二包装之间并将第一和第二包装彼此粘合的粘合部件。 第一封装可以包括具有第一表面和第二表面的第一衬底，第一表面和第二表面彼此面对并且包括形成在第一表面上的焊盘焊盘，形成在第一表面上的第一半导体芯片和封装第一表面的第一密封剂构件， 所述第一半导体芯片并且包括与所述第一半导体芯片间隔开的通孔，并且暴露所述焊盘焊盘和形成在所述第一半导体芯片和所述通孔之间的沟槽，并且其中所述沟槽的至少一部分填充有粘附 会员资料
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公开(公告)号：US11217503B2
公开(公告)日：2022-01-04
申请号：US16748061
申请日：2020-01-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yang Gyoo Jung , Chul Woo Kim , Hyo-Chang Ryu , Seung-Kwan Ryu , Yun Seok Choi
IPC: H01L23/367 , H01L23/42 , H01L25/10 , H01L25/065 , H01L23/498 , H05K1/18 , H01L23/00
Abstract: A semiconductor package includes a substrate and an interposer disposed on the substrate. The interposer comprises a first surface facing the substrate and a second surface facing away from the substrate. A first logic semiconductor chip is disposed on the first surface of the interposer and is spaced apart from the substrate in a first direction orthogonal to an upper surface of the substrate. A first memory package is disposed on the second surface of the interposer. A second memory package is disposed on the second surface of the interposer and is spaced apart from the first memory package in a second direction that is parallel to the upper surface of the substrate. A first heat transfer unit is disposed on a surface of the substrate facing the first logic semiconductor chip. The first heat transfer unit is spaced apart from the first logic semiconductor chip in the first direction.
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公开(公告)号：US10950521B2
公开(公告)日：2021-03-16
申请号：US16566380
申请日：2019-09-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Min-Ok Na , Jongkook Kim , Hyo-Chang Ryu , Jin-woo Park , BongJin Son , Jangwoo Lee
IPC: H01L23/373 , H01L23/367 , H01L21/56 , H01L25/10 , H01L25/00 , H01L25/065 , H01L23/498 , H01L23/50 , H01L23/00
Abstract: Provided are a thermal interface material layer and a package-on-package device including the same. The package-on-package device may include a thermal interface material layer interposed between lower and upper semiconductor packages and configured to have a specific physical property. Accordingly, it is possible to prevent a crack from occurring in a lower semiconductor chip, when a solder ball joint process is performed to mount the upper semiconductor package on the lower semiconductor package.
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