公开(公告)号：US20190355825A1

公开(公告)日：2019-11-21

申请号：US16214537

申请日：2018-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong Hyuk YIM ,  Kug Hwan KIM ,  Wan Don KIM ,  Jung Min PARK ,  Jong Ho PARK ,  Byoung Hoon LEE ,  Yong Ho HA ,  Sang Jin HYUN ,  Hye Ri HONG

IPC: H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78 ,  H01L27/092

Abstract: A semiconductor device according to an example embodiment of the present inventive concept includes a substrate having a first region and a second region horizontally separate from the first region; a first gate line in the first region, the first gate line including a first lower work function layer and a first upper work function layer disposed on the first lower work function layer; and a second gate line including a second lower work function layer in the second region, the second gate line having a width in a first, horizontal direction equal to or narrower than a width of the first gate line in the first direction, wherein an uppermost end of the first upper work function layer and an uppermost end of the second lower work function layer are each located at a vertical level higher than an uppermost end of the first lower work function layer with respect to a second direction perpendicular to the first direction.

公开(公告)号：US20240164094A1

公开(公告)日：2024-05-16

申请号：US18479591

申请日：2023-10-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-Sung KIM ,  Jung Min PARK ,  Bong Jin KUH ,  Yong Ho HA

IPC: H10B41/27 ,  H01L21/28 ,  H01L25/065 ,  H01L29/51 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

CPC classification number: H10B41/27 ,  H01L25/0652 ,  H01L29/40111 ,  H01L29/516 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06506

Abstract: A semiconductor memory device comprises, a substrate, a mold structure including gate electrodes and mold insulating films alternately stacked on the substrate, and a channel structure penetrating the mold structure, wherein the channel structure comprises a semiconductor pattern and a dielectric film on the semiconductor pattern, wherein the dielectric film comprises a first crystalline film in contact with the gate electrodes and a second crystalline film between the first crystalline film and the semiconductor pattern, wherein the first crystalline film includes a first matrix and a first impurity and the second crystalline film includes a second matrix and a second impurity, wherein each of the first matrix and the second matrix comprises at least one of HfO2, HfxZr1-xO2 (0.5

公开(公告)号：US20180261460A1

公开(公告)日：2018-09-13

申请号：US15825135

申请日：2017-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon Tae HWANG ,  Moon Kyun SONG ,  Nam Gyu CHO ,  Kyu Min LEE ,  Soo Jung CHOI ,  Yong Ho HA ,  Sang Jin HYUN

IPC: H01L21/28 ,  H01L29/51 ,  H01L21/02

Abstract: Semiconductor devices and methods for fabricating the same are provided. A semiconductor device may include a substrate including first and second regions, a first interface film disposed on the substrate in the first region, a second interface film disposed on the substrate in the second region, a dielectric film disposed on the first and second interface films, a first metal film disposed on the dielectric film in the first region, and a second metal film disposed on the dielectric film in the second region. The first and second interface films may comprise an oxide of the substrate, the first and second metal films may comprise different materials, and the first and second interface films may have different thicknesses. Channels may be provided in the first and second regions, and the channels may be fin-shaped or wire-shaped. The metal films may have different oxygen content.