公开(公告)号：US20220319916A1

公开(公告)日：2022-10-06

申请号：US17838740

申请日：2022-06-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Won Keun CHUNG ,  Joon Gon LEE ,  Rak Hwan KIM ,  Chung Hwan SHIN ,  Do Sun LEE ,  Nam Gyu CHO

IPC: H01L21/768

Abstract: A semiconductor device includes a first interlayer insulating film; a conductive connection structure provided in the first interlayer insulating film; a second interlayer insulating film provided on the first interlayer insulating film; a wiring structure provided in the second interlayer insulating film and connected to the conductive connection structure; and an insertion liner interposed between an upper surface of the conductive connection structure and the wiring structure, the insertion liner including carbon.

公开(公告)号：US20220285518A1

公开(公告)日：2022-09-08

申请号：US17826380

申请日：2022-05-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Nam Gyu CHO ,  Rak Hwan KIM ,  Hyeok-Jun SON ,  Do Sun LEE ,  Won Keun CHUNG

IPC: H01L29/49 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L21/311 ,  H01L29/786

Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a fin-type pattern extending in a first direction; a gate electrode extending in a second direction over the fin-type pattern, the second direction being different from the first direction; spacers on sidewalls of the gate electrode; a capping structure on the gate electrode and the spacers, the capping structure including a first capping pattern and a second capping pattern, the second capping pattern being on the first capping pattern; and an interlayer insulating film surrounding sidewalls of each of the spacers and sidewalls of the capping structure, the interlayer insulating film being in contact with the first capping pattern.

公开(公告)号：US20210210613A1

公开(公告)日：2021-07-08

申请号：US17015296

申请日：2020-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Nam Gyu CHO ,  Rak Hwan KIM ,  Hyeok-Jun SON ,  Do Sun LEE ,  Won Keun CHUNG

IPC: H01L29/49 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/28 ,  H01L21/311 ,  H01L29/66

Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a fin-type pattern extending in a first direction; a gate electrode extending in a second direction over the fin-type pattern, the second direction being different from the first direction; spacers on sidewalls of the gate electrode; a capping structure on the gate electrode and the spacers, the capping structure including a first capping pattern and a second capping pattern, the second capping pattern being on the first capping pattern; and an interlayer insulating film surrounding sidewalls of each of the spacers and sidewalls of the capping structure, the interlayer insulating film being in contact with the first capping pattern.

公开(公告)号：US20240128347A1

公开(公告)日：2024-04-18

申请号：US18397700

申请日：2023-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Nam Gyu CHO ,  Rak Hwan KIM ,  Hyeok-Jun SON ,  Do Sun LEE ,  Won Keun CHUNG

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/311 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/4983 ,  H01L21/28132 ,  H01L21/31111 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78696

Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a fin-type pattern extending in a first direction; a gate electrode extending in a second direction over the fin-type pattern, the second direction being different from the first direction; spacers on sidewalls of the gate electrode; a capping structure on the gate electrode and the spacers, the capping structure including a first capping pattern and a second capping pattern, the second capping pattern being on the first capping pattern; and an interlayer insulating film surrounding sidewalls of each of the spacers and sidewalls of the capping structure, the interlayer insulating film being in contact with the first capping pattern.

公开(公告)号：US20230378263A1

公开(公告)日：2023-11-23

申请号：US18085886

申请日：2022-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin Kyu JANG ,  Byoung Hoon LEE ,  Chan Hyeong LEE ,  Nam Gyu CHO

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L29/775

CPC classification number: H01L29/0673 ,  H01L29/4236 ,  H01L29/6656 ,  H01L29/78696 ,  H01L29/775

Abstract: A semiconductor device includes an active pattern; gate spacers on the active pattern defining a gate trench; a gate insulating layer along a sidewall and a bottom surface of the gate trench; a first conductive layer on the gate insulating layer; a second conductive layer on the first conductive layer in the gate trench; a third conductive layer on the second conductive layer in the gate trench and including a first portion between parts of the second conductive layer, and a second portion on the first portion and in contact with an upper surface of the second conductive layer; and a capping pattern on the second and third conductive layers and including a portion between the gate insulating layer and the second portion, and in contact with a sidewall of the second portion, wherein a width of the second portion is greater than a width of the first portion.

公开(公告)号：US20180261460A1

公开(公告)日：2018-09-13

申请号：US15825135

申请日：2017-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon Tae HWANG ,  Moon Kyun SONG ,  Nam Gyu CHO ,  Kyu Min LEE ,  Soo Jung CHOI ,  Yong Ho HA ,  Sang Jin HYUN

IPC: H01L21/28 ,  H01L29/51 ,  H01L21/02

Abstract: Semiconductor devices and methods for fabricating the same are provided. A semiconductor device may include a substrate including first and second regions, a first interface film disposed on the substrate in the first region, a second interface film disposed on the substrate in the second region, a dielectric film disposed on the first and second interface films, a first metal film disposed on the dielectric film in the first region, and a second metal film disposed on the dielectric film in the second region. The first and second interface films may comprise an oxide of the substrate, the first and second metal films may comprise different materials, and the first and second interface films may have different thicknesses. Channels may be provided in the first and second regions, and the channels may be fin-shaped or wire-shaped. The metal films may have different oxygen content.