公开(公告)号：US20150325274A1

公开(公告)日：2015-11-12

申请号：US14644339

申请日：2015-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong SHIM ,  Seung-Jun BAE ,  Won-Joo YUN

IPC: G11C7/10

CPC classification number: G11C7/1084 ,  G11C7/1054

Abstract: An input buffer includes a first buffer, a feedback circuit and a second buffer circuit. The feedback circuit includes a feedback resistor and a feedback inverter. The first buffer may be configured to output an amplification signal to an output node of the first buffer based on an input signal. The feedback circuit connected to the output node of the first buffer may be configured to control the amplification signal. The second buffer circuit may be configured to output a buffer output signal by buffering the amplification signal. The feedback resistor may receive the amplification signal from the output node of the first buffer and provide a feedback signal to a feedback node. The feedback inverter is connected between the feedback node and the output node. The feedback inverter may be configured to control the amplification signal based on the feedback signal.

Abstract translation: 输入缓冲器包括第一缓冲器，反馈电路和第二缓冲电路。 反馈电路包括反馈电阻和反馈反馈器。 第一缓冲器可以被配置为基于输入信号将放大信号输出到第一缓冲器的输出节点。 连接到第一缓冲器的输出节点的反馈电路可以被配置为控制放大信号。 第二缓冲电路可以被配置为通过缓冲放大信号来输出缓冲器输出信号。 反馈电阻器可以从第一缓冲器的输出节点接收放大信号，并向反馈节点提供反馈信号。 反馈逆变器连接在反馈节点和输出节点之间。 反馈反相器可以被配置为基于反馈信号来控制放大信号。

公开(公告)号：US20160105165A1

公开(公告)日：2016-04-14

申请号：US14699290

申请日：2015-04-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong SHIM ,  Won-Joo YUN

IPC: H03K3/017 ,  H03K3/86 ,  G04F10/00 ,  H03K3/037

CPC classification number: G04F10/005 ,  H03K5/135 ,  H03K5/1565

Abstract: In a duty cycle error detection device, a first digital code generator is configured to generate high and low codes corresponding to a lengths of high level low level periods, respectively, of a clock signal, generate a sign signal representing the longer period between the high level period and the low level period, and output one of the high and low digital codes corresponding to the shorter period as a first digital code. A clock delay circuit is configured to generate a delay clock signal by delaying the clock signal for a time corresponding to the first digital code, and a second digital code generator is configured to generate a duty error digital code corresponding to a length from a start of the longer period of the delay clock signal to an end of the longer period of the clock signal based on the sign signal.

Abstract translation: 在占空比误差检测装置中，第一数字码发生器被配置为分别产生对应于时钟信号的高电平低电平时段的长度的高和低码，产生表示较高时段之间的较长周期的符号信号 电平周期和低电平周期，并将对应于较短周期的高数字代码和低数字代码之一作为第一数字代码输出。 时钟延迟电路被配置为通过将时钟信号延迟与第一数字代码相对应的时间来产生延迟时钟信号，并且第二数字代码发生器被配置为生成对应于从开始的时间的长度的占空误差数字代码 基于符号信号，延迟时钟信号的较长周期延迟到时钟信号的较长周期的结束。

公开(公告)号：US20140258607A1

公开(公告)日：2014-09-11

申请号：US14197883

申请日：2014-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong SHIM ,  In-Dal SONG

IPC: G11C7/10

CPC classification number: G11C7/1072 ,  G11C7/222 ,  G11C7/225 ,  G11C11/4076

Abstract: A semiconductor memory device and a method of operating the same are provided. The semiconductor memory device includes a buffer that inputs a first signal and outputs a first delay signal, a command decoder that outputs a second signal, a mask pulse signal generator that inputs the first delay signal and the second signal and generates a mask pulse signal, and a signal reshaper that inputs the first delay signal, the second signal and the mask pulse signal and reshapes the first delay signal or the second signal.

Abstract translation: 提供一种半导体存储器件及其操作方法。 半导体存储器件包括输入第一信号并输出​​第一延迟信号的缓冲器，输出第二信号的命令解码器，输入第一延迟信号和第二信号并产生掩模脉冲信号的掩码脉冲信号发生器， 以及输入第一延迟信号，第二信号和掩模脉冲信号并重新形成第一延迟信号或第二信号的信号整形器。

公开(公告)号：US20160156342A1

公开(公告)日：2016-06-02

申请号：US14955051

申请日：2015-12-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won-Joo YUN ,  Yong SHIM

IPC: H03K7/08 ,  H03K5/156 ,  H03L7/085

CPC classification number: H03K7/08 ,  H03K5/1565 ,  H03L7/085

Abstract: An electronic device includes a first duty cycle correction circuit, a delay line, a second duty cycle correction circuit, and a delay control circuit. The first duty cycle correction circuit is configured to detect a duty cycle error of a clock signal by performing time-to-digital conversion on the clock signal, and to generate a corrected clock signal by adjusting a duty cycle of the clock signal based on the duty cycle error of the clock signal. The delay line is configured to generate a delayed corrected clock signal by delaying the corrected clock signal based on a delay control code The second duty cycle correction circuit is configured to detect a duty cycle error of a first output clock signal received through a feedback loop, and to generate a second output clock signal by adjusting duty cycle of the delayed corrected clock signal based on the duty cycle error of the first output clock signal. The delay control circuit is configured to generate the delay control code based on the clock signal and the first output clock signal.

Abstract translation: 电子设备包括第一占空比校正电路，延迟线，第二占空比校正电路和延迟控制电路。 第一占空比校正电路被配置为通过对时钟信号执行时间 - 数字转换来检测时钟信号的占空比误差，并且通过基于时钟信号调整时钟信号的占空比来产生校正时钟信号 时钟信号的占空比误差。 延迟线被配置为通过基于延迟控制码延迟校正的时钟信号来产生延迟的校正时钟信号。第二占空比校正电路被配置为检测通过反馈回路接收的第一输出时钟信号的占空比误差， 并且通过基于第一输出时钟信号的占空比误差来调整延迟校正时钟信号的占空比来产生第二输出时钟信号。 延迟控制电路被配置为基于时钟信号和第一输出时钟信号产生延迟控制代码。

公开(公告)号：US20140254295A1

公开(公告)日：2014-09-11

申请号：US14198028

申请日：2014-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong SHIM ,  In-Dal SONG ,  Young CHOI

IPC: G11C11/4063

CPC classification number: G11C7/1072 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093

Abstract: A memory device is provided. The memory device includes programming first bit data into a plurality of memory cells; identifying target memory cells which are in a first state and whose threshold voltages are equal to or greater than a first voltage from the memory cells programmed with the first bit data; receiving second bit data which is to be programmed into the memory cells; calculating a plurality of third bit data by performing a first process on the second bit data; selecting third bit data which changes a largest number of target memory cells from the first state to a second state in response to the memory cells being programmed with each of the plurality of third bit data from the plurality of third bit data; and programming the selected third bit data into the memory cells.

Abstract translation: 提供存储器件。 存储器件包括将第一位数据编程到多个存储器单元中; 识别处于第一状态并且其阈值电压等于或大于来自用第一位数据编程的存储器单元的第一电压的目标存储器单元; 接收要编程到存储器单元中的第二位数据; 通过对所述第二位数据执行第一处理来计算多个第三位数据; 响应于来自多个第三位数据的多个第三位数据中的每一个对存储器单元进行编程，选择将最大数目的目标存储器单元从第一状态改变到第二状态的第三位数据; 并将所选择的第三位数据编程到存储器单元中。