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公开(公告)号：US11728347B2
公开(公告)日：2023-08-15
申请号：US17494275
申请日：2021-10-05
发明人： Weonhong Kim , Pilkyu Kang , Yuichiro Sasaki , Sungkeun Lim , Yongho Ha , Sangjin Hyun , Kughwan Kim , Seungha Oh
IPC分类号： H01L27/12 , H01L21/762 , H01L27/02 , H01L29/78
CPC分类号： H01L27/1203 , H01L21/76224 , H01L27/0203 , H01L27/02 , H01L29/78
摘要： An integrated circuit device includes an embedded insulation layer, a semiconductor layer on the embedded insulation layer, the semiconductor layer having a main surface, and a plurality of fin-type active areas protruding from the main surface to extend in a first horizontal direction and in parallel with one another, a separation insulation layer separating the semiconductor layer into at least two element regions adjacent to each other in a second horizontal direction intersecting the first horizontal direction, source/drain regions on the plurality of fin-type active areas, a first conductive plug on and electrically connected to the source/drain regions, a buried rail electrically connected to the first conductive plug while penetrating through the separation insulation layer and the semiconductor layer, and a power delivery structure arranged in the embedded insulation layer, the power delivery structure being in contact with and electrically connected to the buried rail.
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公开(公告)号：US10164017B2
公开(公告)日：2018-12-25
申请号：US15887773
申请日：2018-02-02
发明人： Yuichiro Sasaki , Bong Soo Kim , Tae Gon Kim , Yoshiya Moriyama , Seung Hyun Song , Alexander Schmidt , Abraham Yoo , Heung Soon Lee , Kyung In Choi
IPC分类号： H01L29/10 , H01L29/08 , H01L29/66 , H01L29/78 , H01L27/092 , H01L21/8238 , H01L21/223 , H01L21/265
摘要： A semiconductor device having an impurity region is provided. The semiconductor device includes a fin active region having protruding regions and a recessed region between the protruding regions. Gate structures overlapping the protruding regions are disposed. An epitaxial layer is disposed in the recessed region to have a height greater than a width. An impurity region is disposed in the fin active region, surrounds side walls and a bottom of the recessed region, has the same conductivity type as a conductivity type of the epitaxial layer, and includes a majority impurity that is different from a majority impurity included in at least a portion of the epitaxial layer.
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公开(公告)号：US09911809B2
公开(公告)日：2018-03-06
申请号：US15424081
申请日：2017-02-03
发明人： Yuichiro Sasaki , Bong Soo Kim , Tae Gon Kim , Yoshiya Moriyama , Seung Hyun Song , Alexander Schmidt , Abraham Yoo , Heung Soon Lee , Kyung In Choi
IPC分类号： H01L29/10 , H01L29/78 , H01L27/092 , H01L29/66 , H01L29/08 , H01L21/8238
CPC分类号： H01L29/1083 , H01L21/2236 , H01L21/26586 , H01L21/823814 , H01L21/823821 , H01L21/823892 , H01L27/0921 , H01L27/0924 , H01L29/0847 , H01L29/66537 , H01L29/66545 , H01L29/66636 , H01L29/66795 , H01L29/7851
摘要： A semiconductor device having an impurity region is provided. The semiconductor device includes a fin active region having protruding regions and a recessed region between the protruding regions. Gate structures overlapping the protruding regions are disposed. An epitaxial layer is disposed in the recessed region to have a height greater than a width. An impurity region is disposed in the fin active region, surrounds side walls and a bottom of the recessed region, has the same conductivity type as a conductivity type of the epitaxial layer, and includes a majority impurity that is different from a majority impurity included in at least a portion of the epitaxial layer.
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公开(公告)号：US10804269B2
公开(公告)日：2020-10-13
申请号：US16419318
申请日：2019-05-22
发明人： Kyungin Choi , Taehyeon Kim , Hongshik Shin , Taegon Kim , Jaeyoung Park , Yuichiro Sasaki
IPC分类号： H01L27/092 , H01L29/66 , H01L29/78 , H01L29/417 , H01L21/225 , H01L21/768 , H01L21/8238 , H01L29/161 , H01L29/165 , H01L21/285
摘要： A method of fabricating a semiconductor device includes pattering an upper portion of a substrate to form a first active pattern, the substrate including a semiconductor element having a first lattice constant, performing a selective epitaxial growth process on an upper portion of the first active pattern to form a first source/drain region, doping the first source/drain region with gallium, performing an annealing process on the first source/drain region doped with gallium, and forming a first contact pattern coupled to the first source/drain region. The first source/drain region includes a semiconductor element having a second lattice constant larger than the first lattice constant.
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公开(公告)号：US10355000B2
公开(公告)日：2019-07-16
申请号：US15793442
申请日：2017-10-25
发明人： Kyungin Choi , Taehyeon Kim , Hongshik Shin , Taegon Kim , Jaeyoung Park , Yuichiro Sasaki
IPC分类号： H01L27/092 , H01L21/82 , H01L21/768 , H01L21/225 , H01L21/8238 , H01L29/66 , H01L29/78 , H01L29/161 , H01L29/165
摘要： A method of fabricating a semiconductor device includes pattering an upper portion of a substrate to form a first active pattern, the substrate including a semiconductor element having a first lattice constant, performing a selective epitaxial growth process on an upper portion of the first active pattern to form a first source/drain region, doping the first source/drain region with gallium, performing an annealing process on the first source/drain region doped with gallium, and forming a first contact pattern coupled to the first source/drain region. The first source/drain region includes a semiconductor element having a second lattice constant larger than the first lattice constant.
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公开(公告)号：US11901356B2
公开(公告)日：2024-02-13
申请号：US16817069
申请日：2020-03-12
发明人： Seungha Oh , Pil-Kyu Kang , Kughwan Kim , Weonhong Kim , Yuichiro Sasaki , Sang Woo Lee , Sungkeun Lim , Yongho Ha , Sangjin Hyun
CPC分类号： H01L27/0688 , H01L23/481 , H10B41/60 , H10B43/20 , H10B63/30 , H10B63/84
摘要： A three-dimensional semiconductor device includes a lower substrate, a plurality of lower transistors disposed on the lower substrate, an upper substrate disposed on the lower transistors, a plurality of lower conductive lines disposed between the lower transistors and the upper substrate, and a plurality of upper transistors disposed on the upper substrate. At least one of the lower transistors is connected to a corresponding one of the lower conductive lines. Each of the upper transistors includes an upper gate electrode disposed on the upper substrate, a first upper source/drain pattern disposed in the upper substrate at a first side of the upper gate electrode, and a second upper source/drain pattern disposed in the upper substrate at a second, opposing side of the upper gate electrode. The upper gate electrode includes silicon germanium (SiGe).
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公开(公告)号：US11610838B2
公开(公告)日：2023-03-21
申请号：US17367773
申请日：2021-07-06
发明人： Yuichiro Sasaki , Sungkeun Lim , Pil-Kyu Kang , Weonhong Kim , Seungha Oh , Yongho Ha , Sangjin Hyun
IPC分类号： H01L23/522 , H01L23/50 , H01L23/528
摘要： A semiconductor device includes a semiconductor layer having a first surface and a second surface opposite to the first surface, an active pattern on the first surface, the active pattern including a source/drain region, a power rail electrically connected to the source/drain region, and a power delivery network on the second surface, the power delivery network electrically connected to the power rail. The semiconductor layer includes an etch stop dopant, and the etch stop dopant has a maximum concentration at the second surface.
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公开(公告)号：US11322494B2
公开(公告)日：2022-05-03
申请号：US17015307
申请日：2020-09-09
发明人： Kyungin Choi , Taehyeon Kim , Hongshik Shin , Taegon Kim , Jaeyoung Park , Yuichiro Sasaki
IPC分类号： H01L27/092 , H01L21/768 , H01L21/8238 , H01L29/66 , H01L29/78 , H01L29/417 , H01L21/225 , H01L29/161 , H01L29/165 , H01L21/285
摘要： A method of fabricating a semiconductor device includes pattering an upper portion of a substrate to form a first active pattern, the substrate including a semiconductor element having a first lattice constant, performing a selective epitaxial growth process on an upper portion of the first active pattern to form a first source/drain region, doping the first source/drain region with gallium, performing an annealing process on the first source/drain region doped with gallium, and forming a first contact pattern coupled to the first source/drain region. The first source/drain region includes a semiconductor element having a second lattice constant larger than the first lattice constant.
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公开(公告)号：US11177286B2
公开(公告)日：2021-11-16
申请号：US16807410
申请日：2020-03-03
发明人： Weonhong Kim , Pilkyu Kang , Yuichiro Sasaki , Sungkeun Lim , Yongho Ha , Sangjin Hyun , Kughwan Kim , Seungha Oh
IPC分类号： H01L27/12 , H01L29/78 , H01L21/762 , H01L27/02
摘要： An integrated circuit device includes an embedded insulation layer, a semiconductor layer on the embedded insulation layer, the semiconductor layer having a main surface, and a plurality of fin-type active areas protruding from the main surface to extend in a first horizontal direction and in parallel with one another, a separation insulation layer separating the semiconductor layer into at least two element regions adjacent to each other in a second horizontal direction intersecting the first horizontal direction, source/drain regions on the plurality of fin-type active areas, a first conductive plug on and electrically connected to the source/drain regions, a buried rail electrically connected to the first conductive plug while penetrating through the separation insulation layer and the semiconductor layer, and a power delivery structure arranged in the embedded insulation layer, the power delivery structure being in contact with and electrically connected to the buried rail.
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公开(公告)号：US11121080B2
公开(公告)日：2021-09-14
申请号：US16809788
申请日：2020-03-05
发明人： Yuichiro Sasaki , Sungkeun Lim , Pil-Kyu Kang , Weonhong Kim , Seungha Oh , Yongho Ha , Sangjin Hyun
IPC分类号： H01L23/522 , H01L23/50 , H01L23/528
摘要： A semiconductor device includes a semiconductor layer having a first surface and a second surface opposite to the first surface, an active pattern on the first surface, the active pattern including a source/drain region, a power rail electrically connected to the source/drain region, and a power delivery network on the second surface, the power delivery network electrically connected to the power rail. The semiconductor layer includes an etch stop dopant, and the etch stop dopant has a maximum concentration at the second surface.
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