公开(公告)号：US11075610B2

公开(公告)日：2021-07-27

申请号：US16654558

申请日：2019-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghwan Hong ,  Yoo-Chang Sung ,  Wangsoo Kim ,  Indal Song

IPC: H03F3/45 ,  H03G5/16 ,  H03F3/68 ,  H03F1/26 ,  H04B1/16

Abstract: A receiver includes an amplifier that receives a transmission signal and amplifies a first voltage difference between the transmission signal and a reference signal to generate a first output signal and a second output signal at a first node and a second node. An equalizer is provided, which is connected to the first node and the second node and receives the transmission signal. The equalizer compensates a common-mode offset between the first output signal and the second output signal based on a second voltage difference between an average voltage level of the transmission signal and the reference signal.

公开(公告)号：US11874784B2

公开(公告)日：2024-01-16

申请号：US18089148

申请日：2022-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heon Su Jeong ,  Hangi Jung ,  Wangsoo Kim ,  Hae Young Chung

IPC: G06F13/16 ,  G06F13/40 ,  G11C7/22 ,  G11C7/10 ,  G11C8/18

CPC classification number: G06F13/1673 ,  G06F13/4086 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/1096 ,  G11C7/222 ,  G11C7/225 ,  G11C8/18 ,  G11C2207/2254

Abstract: A memory device of a memory module includes a CA buffer that receives a command/address (CA) signal through a bus shared by a memory device different from the memory device of the memory module, and a calibration logic circuit that identifies location information of the memory device on the bus. The memory device recognizes its own location on a bus in a memory module to perform self-calibration, and thus, the memory device appropriately operates even under an operation condition varying depending on a location in the memory module.

公开(公告)号：US20200313638A1

公开(公告)日：2020-10-01

申请号：US16654558

申请日：2019-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghwan Hong ,  Yoo-Chang Sung ,  Wangsoo Kim ,  Indal Song

IPC: H03G5/16 ,  H03F3/45 ,  H03F3/68 ,  H03F1/26 ,  H04B1/16

Abstract: A receiver includes an amplifier that receives a transmission signal and amplifies a first voltage difference between the transmission signal and a reference signal to generate a first output signal and a second output signal at a first node and a second node. An equalizer is provided, which is connected to the first node and the second node and receives the transmission signal. The equalizer compensates a common-mode offset between the first output signal and the second output signal based on a second voltage difference between an average voltage level of the transmission signal and the reference signal.

公开(公告)号：US20240096384A1

公开(公告)日：2024-03-21

申请号：US18325443

申请日：2023-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wangsoo Kim ,  Minkyung Kim ,  Wonmuk Lim

IPC: G11C7/20 ,  G11C7/02 ,  G11C7/14

CPC classification number: G11C7/20 ,  G11C7/02 ,  G11C7/14

Abstract: A preamble detection circuit, an operating method thereof, and a memory device are provided. The preamble detection circuit includes a comparison circuit configured to compare a level of a data strobe signal with a level of a reference voltage and to output a comparison signal, and a reset signal generation circuit configured to output a reset signal having a pulse width corresponding to a preamble period of the data strobe signal based on the comparison signal.

公开(公告)号：US11791791B2

公开(公告)日：2023-10-17

申请号：US17352487

申请日：2021-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghwan Hong ,  Yoo-Chang Sung ,  Wangsoo Kim ,  Indal Song

IPC: H03F3/45 ,  H03G5/16 ,  H03F3/68 ,  H03F1/26 ,  H04B1/16

CPC classification number: H03G5/165 ,  H03F1/26 ,  H03F3/45183 ,  H03F3/68 ,  H04B1/16 ,  H03F2200/129 ,  H03F2200/165 ,  H03F2200/267 ,  H03F2200/375 ,  H03F2203/45212

Abstract: A receiver includes an amplifier that receives a transmission signal and amplifies a first voltage difference between the transmission signal and a reference signal to generate a first output signal and a second output signal at a first node and a second node. An equalizer is provided, which is connected to the first node and the second node and receives the transmission signal. The equalizer compensates a common-mode offset between the first output signal and the second output signal based on a second voltage difference between an average voltage level of the transmission signal and the reference signal.

公开(公告)号：US11567886B2

公开(公告)日：2023-01-31

申请号：US17008121

申请日：2020-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heon Su Jeong ,  Hangi Jung ,  Wangsoo Kim ,  Hae Young Chung

IPC: G06F13/16 ,  G06F13/40 ,  G11C7/22 ,  G11C7/10 ,  G11C8/18

Abstract: A memory device of a memory module includes a CA buffer that receives a command/address (CA) signal through a bus shared by a memory device different from the memory device of the memory module, and a calibration logic circuit that identifies location information of the memory device on the bus. The memory device recognizes its own location on a bus in a memory module to perform self-calibration, and thus, the memory device appropriately operates even under an operation condition varying depending on a location in the memory module.

公开(公告)号：US20210313945A1

公开(公告)日：2021-10-07

申请号：US17352487

申请日：2021-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghwan Hong ,  Yoo-Chang Sung ,  Wangsoo Kim ,  Indal Song

IPC: H03G5/16 ,  H03F3/45 ,  H03F3/68 ,  H03F1/26 ,  H04B1/16

Abstract: A receiver includes an amplifier that receives a transmission signal and amplifies a first voltage difference between the transmission signal and a reference signal to generate a first output signal and a second output signal at a first node and a second node. An equalizer is provided, which is connected to the first node and the second node and receives the transmission signal. The equalizer compensates a common-mode offset between the first output signal and the second output signal based on a second voltage difference between an average voltage level of the transmission signal and the reference signal.

公开(公告)号：US20240111695A1

公开(公告)日：2024-04-04

申请号：US18538263

申请日：2023-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heon Su JEONG ,  Hangi Jung ,  Wangsoo Kim ,  Hae Young Chung

IPC: G06F13/16 ,  G06F13/40 ,  G11C7/10 ,  G11C7/22 ,  G11C8/18

CPC classification number: G06F13/1673 ,  G06F13/4086 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/1096 ,  G11C7/222 ,  G11C7/225 ,  G11C8/18 ,  G11C2207/2254

Abstract: A memory device of a memory module includes a CA buffer that receives a command/address (CA) signal through a bus shared by a memory device different from the memory device of the memory module, and a calibration logic circuit that identifies location information of the memory device on the bus. The memory device recognizes its own location on a bus in a memory module to perform self-calibration, and thus, the memory device appropriately operates even under an operation condition varying depending on a location in the memory module.

公开(公告)号：US20210141747A1

公开(公告)日：2021-05-13

申请号：US17008121

申请日：2020-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heon Su JEONG ,  Hangi JUNG ,  Wangsoo Kim ,  Hae Young CHUNG

IPC: G06F13/16 ,  G06F13/40 ,  G11C7/22 ,  G11C7/10 ,  G11C8/18

Abstract: A memory device of a memory module includes a CA buffer that receives a command/address (CA) signal through a bus shared by a memory device different from the memory device of the memory module, and a calibration logic circuit that identifies location information of the memory device on the bus. The memory device recognizes its own location on a bus in a memory module to perform self-calibration, and thus, the memory device appropriately operates even under an operation condition varying depending on a location in the memory module.

公开(公告)号：US10367490B2

公开(公告)日：2019-07-30

申请号：US16026145

申请日：2018-07-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wangsoo Kim ,  Hangi Jung ,  Kiduk Park ,  Yoo-Chang Sung ,  Jae-Hun Jung ,  Cheongryong Cho ,  Hun-Dae Choi

IPC: H03K5/13 ,  H04B1/04 ,  H03K5/00

Abstract: An electronic circuit may include a driver, a delay circuit, a strength control circuit, and an adder circuit. The driver may generate a second signal based on a first signal. The delay circuit may delay the first signal by as much as a reference time, to generate a third signal. The strength control circuit may adjust an amplitude of the third signal to generate a fourth signal. The adder circuit may add the second signal and the fourth signal to generate a fifth signal. In a first time interval determined based on the reference time, an amplitude of the fifth signal may be greater than an amplitude of the second signal. In a second time interval except for the first time interval, the amplitude of the fifth signal may be smaller than the amplitude of the second signal. In the second time interval, the amplitude of the fifth signal may be smaller than an amplitude of the first signal.