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    METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT DEVICE
    1.
    发明公开
    METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT DEVICE 审中-公开

    公开(公告)号：US20240339450A1

    公开(公告)日：2024-10-10

    申请号：US18746928

    申请日：2024-06-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Junggil YANG ,  Minju KIM ,  Donghyi KOH

    IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78

    CPC classification number: H01L27/0886 ,  H01L29/0673 ,  H01L29/7851

    Abstract: An integrated circuit device including a substrate including first and second device regions; a first fin active region on the first device region; a second fin active region on the second device region; an isolation film covering side walls of the active regions; gate cut insulating patterns on the isolation film on the device regions; a gate line extending on the fin active regions, the gate line having a length limited by the gate cut insulating patterns; and an inter-region insulating pattern on the isolation film between the fin active regions and at least partially penetrating the gate line in a vertical direction, wherein the inter-region insulating pattern has a bottom surface proximate to the substrate, a top surface distal to the substrate, and a side wall linearly extending from the bottom to the top surface.

    INTEGRATED CIRCUIT DEVICE
    2.
    发明公开
    INTEGRATED CIRCUIT DEVICE 审中-公开

    公开(公告)号：US20240030283A1

    公开(公告)日：2024-01-25

    申请号：US18224745

    申请日：2023-07-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jooho JUNG ,  Junggil YANG ,  Deokhwan KIM

    IPC: H01L29/06 ,  H01L27/092 ,  H01L29/66 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

    CPC classification number: H01L29/0649 ,  H01L27/092 ,  H01L29/66545 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

    Abstract: An integrated circuit device includes: a fin-type active region protruding from a substrate and extending in a first lateral direction, wherein the fin-type active region includes a first sub-fin-type active region, a second sub-fin-type active region, and a third sub-fin-type active region that is disposed between the first sub-fin-type active region and the second sub-fin-type active region; a first gate line extending in a second lateral direction on the first sub-fin-type active region, wherein the second lateral direction intersects with the first lateral direction; a second gate line extending in the second lateral direction on the second sub-fin-type active region; a diffusion break structure passing through a portion of the third sub-fin-type active region in a vertical direction, wherein the diffusion break structure has a groove portion in an upper portion thereof; and a crack filler filling the groove portion.

    SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220037494A1

    公开(公告)日：2022-02-03

    申请号：US17189615

    申请日：2021-03-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junbeom PARK ,  Sangsu KIM ,  Junggil YANG

    IPC: H01L29/423 ,  H01L29/417

    Abstract: A semiconductor device includes a first source/drain structure having a first length in a horizontal direction, as viewed in a planar cross-sectional view, the horizontal direction being perpendicular to a vertical direction, a second source/drain structure having a second length in the horizontal direction, as viewed in the planar cross-sectional view, the second length being less than the first length, channels extending between the first source/drain structure and the second source/drain structure, the channels being spaced apart from each other in the vertical direction, at least one sacrificial pattern between adjacent ones of the channels, and a trench penetrating the channels and the at least one sacrificial pattern.

    INTEGRATED CIRCUIT DEVICE
    4.
    发明公开
    INTEGRATED CIRCUIT DEVICE 审中-公开

    公开(公告)号：US20240321992A1

    公开(公告)日：2024-09-26

    申请号：US18531071

    申请日：2023-12-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seungpyo HONG ,  Beomjin PARK ,  Junggil YANG

    IPC: H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775

    CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775 ,  H01L2029/42388

    Abstract: An integrated circuit device includes fin-type active regions extending in a first lateral direction on a substrate, a device isolation film covering sidewalls of the fin-type active regions, a gate line on the fin-type active regions and the device isolation film, nanosheet stacks on a fin top surface of each of the fin-type active regions, each nanosheet stack including at least one nanosheet and being surrounded by the gate line, a gate cut insulating portion on the device isolation film and facing an end sidewall of the gate line in a second lateral direction, and a corner insulating spacer between a first nanosheet stack of the nanosheet stacks and the gate cut insulating portion and between the device isolation film and the gate line, the first nanosheet stack being closest to the gate cut insulating portion in the second lateral direction.

    SEMICONDUCTOR DEVICE
    6.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230298945A1

    公开(公告)日：2023-09-21

    申请号：US17961172

    申请日：2022-10-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junggil YANG ,  Inhyun SONG ,  Jooho JUNG

    IPC: H01L21/8238

    CPC classification number: H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878

    Abstract: A semiconductor device may include first and second channel patterns, which are provided on first and second active patterns, respectively, and include first semiconductor patterns and second semiconductor patterns, respectively, and a gate electrode crossing over the first and second channel patterns in a first direction. The gate electrode may include first and second outer gate electrodes, which are provided on the uppermost ones of the first and second semiconductor patterns, respectively, and each of which includes a first metal pattern, a second metal pattern thinner than the first metal pattern, and a filling metal pattern sequentially stacked. A third metal pattern may be further provided between the first metal pattern and the first semiconductor patterns. The third and second metal patterns may include p- and n-type work function metals, respectively. The first and second metal patterns of the second outer gate electrode may have coplanar topmost surfaces.

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    8.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20160372474A1

    公开(公告)日：2016-12-22

    申请号：US15249518

    申请日：2016-08-29

    Applicant: Samsung Electronics Co. Ltd.

    Inventor： Junggil YANG ,  SANGSU KIM ,  TaeYong KWON ,  SUNG GI HUR

    IPC: H01L27/092 ,  H01L21/306 ,  H01L21/8238

    CPC classification number: H01L27/0924 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0922 ,  H01L29/1054 ,  H01L29/42392

    Abstract: A method of fabricating a semiconductor device includes preparing a substrate including a first region and a second region, sequentially forming a first semiconductor layer and a second semiconductor layer on the first and second regions, patterning the first and second semiconductor layers to form a lower semiconductor pattern and an upper semiconductor pattern on each of the first and second regions, selectively removing the lower semiconductor pattern on the second region to form a gap region, and forming gate electrodes at the first and second regions, respectively.

    Abstract translation: 制造半导体器件的方法包括制备包括第一区域和第二区域的衬底，在第一和第二区域上依次形成第一半导体层和第二半导体层，图案化第一和第二半导体层以形成下部半导体 图案和上半导体图案，选择性地去除第二区域上的下半导体图案以形成间隙区域，以及分别在第一和第二区域形成栅电极。

    SEMICONDUCTOR DEVICES
    9.
    发明申请
    SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20220238723A1

    公开(公告)日：2022-07-28

    申请号：US17398504

    申请日：2021-08-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Soojin JEONG ,  Myunggil KANG ,  Junggil YANG ,  Junbeom PARK

    IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66

    Abstract: A semiconductor device includes a first source/drain, a second source/drain isolated from direct contact with the first source/drain in a horizontal direction, a channel extending between the first source/drain and the second source/drain, a gate surrounding the channel, an upper inner spacer between the gate and the first source/drain and above the channel, and a lower inner spacer between the gate and the first source/drain and under the channel, in which the channel includes a base portion extending between the first source/drain and the second source/drain, an upper protrusion portion protruding upward from a top surface of the base portion, and a lower protrusion portion protruding downward from a bottom surface of the base portion, and a direction in which a top end of the upper protrusion portion is isolated from direct contact with a bottom end of the lower protrusion portion is oblique with respect to a vertical direction.

    METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
    10.
    发明申请
    METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220140081A1

    公开(公告)日：2022-05-05

    申请号：US17577595

    申请日：2022-01-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sangsu KIM ,  Junbeom PARK ,  Junggil YANG

    IPC: H01L29/10 ,  H01L29/786 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423

    Abstract: A semiconductor device including an active pattern on a substrate and extending lengthwise in a first direction parallel to an upper surface of the substrate; a gate structure on the active pattern, the gate structure extending in a second direction parallel to the upper surface of the substrate and crossing the first direction; channels spaced apart from each other along a third direction perpendicular to the upper surface of the substrate, each of the channels extending through the gate structure along the first direction; a source/drain layer on a portion of the active pattern adjacent to the gate structure in the first direction, the source/drain layer contacting the channels; inner spacers between the gate structure and the source/drain layer, the inner spacers contacting the source/drain layer; and channel connection portions between each of the inner spacers and the gate structure, the channel connection portions connecting the channels with each other.

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