公开(公告)号：US07271614B2

公开(公告)日：2007-09-18

申请号：US11094974

申请日：2005-03-31

申请人： Samuel Khoo ,  John C. Kriz ,  Bernard L. Morris

发明人： Samuel Khoo ,  John C. Kriz ,  Bernard L. Morris

IPC分类号： H03K17/16

CPC分类号： H03K19/018507 ,  H03K19/00315

摘要： A buffer circuit is configured to generate an output signal which is a function of an input signal received by the buffer circuit, the buffer circuit being selectively operative in one of at least two modes in response to a control signal. In a first mode, the buffer circuit is configured to provide a low output impedance, characteristic of a digital buffer. In a second mode, the buffer circuit is configured to limit an output current of the buffer circuit. The control signal is indicative of a level of the output signal of the buffer circuit.

摘要翻译： 缓冲电路被配置为产生作为由缓冲电路接收的输入信号的函数的输出信号，缓冲电路响应于控制信号选择性地以至少两种模式之一操作。 在第一模式中，缓冲电路被配置为提供数字缓冲器的特性的低输出阻抗。 在第二模式中，缓冲电路被配置为限制缓冲电路的输出电流。 控制信号表示缓冲电路的输出信号的电平。

公开(公告)号：US07511550B2

公开(公告)日：2009-03-31

申请号：US11535198

申请日：2006-09-26

申请人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris ,  Yehuda Smooha

发明人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris ,  Yehuda Smooha

IPC分类号： H03K5/08

CPC分类号： H03K19/0016 ,  H01L27/0251 ,  H03K19/00315

摘要： An IC having improved reliability includes at least first and second circuit blocks and at least first and second power domains, the first circuit block being connected to the first power domain and the second circuit block being connected to the second power domain. The IC further includes at least one control circuit configured to generate at least first and second control signals. The first control signal is operative to selectively connect the first power domain to a first voltage supply, and the second control signal is operative to selectively connect the second power domain to a second voltage supply. The IC includes at least first and second clamp circuits, the first clamp circuit being connected to the first power domain, the second clamp circuit being connected to the second power domain. Each of the clamp circuits is operative to prevent a voltage on a corresponding power domain from rising above a prescribed voltage level for the corresponding power domain.

摘要翻译： 具有改进的可靠性的IC至少包括第一和第二电路块以及至少第一和第二电力域，第一电路块连接到第一电力域，第二电路块连接到第二电力域。 IC还包括被配置为产生至少第一和第二控制信号的至少一个控制电路。 第一控制信号用于选择性地将第一功率域连接到第一电压源，并且第二控制信号用于选择性地将第二功率域连接到第二电压源。 IC包括至少第一和第二钳位电路，第一钳位电路连接到第一电源域，第二钳位电路连接到第二电源域。 每个钳位电路可操作以防止相应功率域上的电压升高到对应功率域的规定电压电平以上。

公开(公告)号：US07382168B2

公开(公告)日：2008-06-03

申请号：US11215663

申请日：2005-08-30

申请人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris ,  Yehuda Smooha

发明人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris ,  Yehuda Smooha

IPC分类号： H03B1/00

CPC分类号： H03K19/018585 ,  H03K19/018521 ,  H03K19/018592

摘要： A buffer circuit operative at multiple power supply voltage levels includes first and second buffers, the first buffer being configured for operation with a first voltage source and the second buffer being operative with a second voltage source. The buffer circuit further includes a controllable isolation circuit. An output of the first buffer connects to an external pad of the buffer circuit, and an output of the second buffer connects to the pad via the isolation circuit. The buffer circuit is selectively operative in at least a first mode or a second mode in response to at least a first control signal. The isolation circuit is operative in the first mode to substantially isolate the second buffer from the external pad and is operative in the second mode to connect the output of the second buffer to the external pad.

摘要翻译： 在多个电源电压电平下工作的缓冲电路包括第一和第二缓冲器，第一缓冲器被配置为与第一电压源一起操作，第二缓冲器与第二电压源一起工作。 缓冲电路还包括可控隔离电路。 第一缓冲器的输出连接到缓冲电路的外部焊盘，第二缓冲器的输出经由隔离电路连接到焊盘。 响应于至少第一控制信号，缓冲电路在至少第一模式或第二模式中选择性地工作。 隔离电路在第一模式下工作，以将第二缓冲器与外部焊盘基本隔离，并且在第二模式下工作，以将第二缓冲器的输出连接到外部焊盘。

公开(公告)号：US20080074814A1

公开(公告)日：2008-03-27

申请号：US11535719

申请日：2006-09-27

申请人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris ,  Yehuda Smooha

发明人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris ,  Yehuda Smooha

IPC分类号： H02H9/00

CPC分类号： H03K17/063

摘要： A circuit for selectively bypassing a capacitive element includes at least one NMOS device selectively connectable across the capacitive element to be bypassed, and at least first and second PMOS devices. The PMOS devices are selectively connectable together in series across the capacitive element to be bypassed. The NMOS device provides a first bypass path and the first and second PMOS devices collectively provide a second bypass path.

摘要翻译： 用于选择性地绕过电容元件的电路包括至少一个可选择地连接在待旁路的电容元件上的NMOS器件，以及至少第一和第二PMOS器件。 PMOS器件可选择性地连接在电容元件上串联在一起以被旁路。 NMOS器件提供第一旁路路径，并且第一和第二PMOS器件共同提供第二旁路路径。

公开(公告)号：US07642807B2

公开(公告)日：2010-01-05

申请号：US11768496

申请日：2007-06-26

申请人： Dipankar Bhattacharya ,  Gregg R. Harleman ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris

发明人： Dipankar Bhattacharya ,  Gregg R. Harleman ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris

IPC分类号： H03K17/16

CPC分类号： H03K19/00376

摘要： A compensated buffer circuit operative in one of at least a first mode and a second mode includes a plurality of output blocks and a plurality of predrivers, each of the predrivers having an output connected to an input of a corresponding one of the output blocks. Respective outputs of the output blocks are connected together and form an output of the buffer circuit. The output blocks are arranged in a sequence and are binary weighted such that a drive strength of a given one of the output blocks is about twice as large as a drive strength of an output block immediately preceding the given output block. Each of the predrivers selectively enables the corresponding output block connected thereto as a function of a control signal supplied to the predriver for compensating the buffer circuit for PVT variations to which the buffer circuit may be subjected. The respective control signals supplied to the predrivers collectively represent a binary code word, the binary code word in the second mode being equivalent to an arithmetic shift of the binary code word in the first mode.

摘要翻译： 以至少第一模式和第二模式之一工作的补偿缓冲器电路包括多个输出块和多个预驱动器，每个预驱动器具有连接到相应一个输出块的输入的输出。 输出块的各输出端连接在一起形成缓冲电路的输出。 输出块按顺序排列并且被二进制加权，使得给定的一个输出块的驱动强度大约是在给定输出块之前的输出块的驱动强度的两倍。 每个预驱动器根据提供给预驱动器的控制信号选择性地使连接到其上的相应输出块能够补偿用于缓冲电路可能经受的PVT变化的缓冲电路。 提供给预驱动器的各个控制信号共同表示二进制码字，第二模式中的二进制码字等效于第一模式中的二进制码字的算术移位。

公开(公告)号：US20080074171A1

公开(公告)日：2008-03-27

申请号：US11535198

申请日：2006-09-26

申请人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris ,  Yehuda Smooha

发明人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris ,  Yehuda Smooha

IPC分类号： G05F1/10

CPC分类号： H03K19/0016 ,  H01L27/0251 ,  H03K19/00315

摘要： An IC having improved reliability includes at least first and second circuit blocks and at least first and second power domains, the first circuit block being connected to the first power domain and the second circuit block being connected to the second power domain. The IC further includes at least one control circuit configured to generate at least first and second control signals. The first control signal is operative to selectively connect the first power domain to a first voltage supply, and the second control signal is operative to selectively connect the second power domain to a second voltage supply. The IC includes at least first and second clamp circuits, the first clamp circuit being connected to the first power domain, the second clamp circuit being connected to the second power domain. Each of the clamp circuits is operative to prevent a voltage on a corresponding power domain from rising above a prescribed voltage level for the corresponding power domain.

摘要翻译： 具有改进的可靠性的IC至少包括第一和第二电路块以及至少第一和第二电力域，第一电路块连接到第一电力域，第二电路块连接到第二电力域。 IC还包括被配置为产生至少第一和第二控制信号的至少一个控制电路。 第一控制信号用于选择性地将第一功率域连接到第一电压源，并且第二控制信号用于选择性地将第二功率域连接到第二电压源。 IC包括至少第一和第二钳位电路，第一钳位电路连接到第一电源域，第二钳位电路连接到第二电源域。 每个钳位电路可操作以防止相应功率域上的电压升高到对应功率域的规定电压电平以上。

公开(公告)号：US07276957B2

公开(公告)日：2007-10-02

申请号：US11239840

申请日：2005-09-30

申请人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Duane J. Loeper ,  Bernard L. Morris ,  Yehuda Smooha

发明人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Duane J. Loeper ,  Bernard L. Morris ,  Yehuda Smooha

IPC分类号： H03K

CPC分类号： H03K19/00315 ,  H03K2217/0018

摘要： A circuit for defining a voltage potential of a floating well in which is formed at least one metal-oxide-semiconductor device includes a sense circuit operative to detect a voltage at a node to which the floating well is connected and to generate a control signal indicative of whether the voltage at the node is substantially within a voltage range. A lower value of the voltage range is substantially equal to a threshold voltage below a first supply voltage of the circuit. An upper value of the voltage range is substantially equal to a threshold voltage above the first supply voltage. The circuit for defining the voltage potential of the floating well further includes a voltage generator circuit operative to receive the control signal and to generate a bias signal for setting a voltage potential of the well in response to the control signal, the bias signal being controlled throughout the voltage range.

摘要翻译： 用于限定其中形成有至少一个金属氧化物半导体器件的浮动阱的电压电位的电路包括感测电路，其可操作以检测浮动阱连接到的节点处的电压，并产生指示性的控制信号 节点处的电压是否基本上在电压范围内。 电压范围的较低值基本上等于低于电路的第一电源电压的阈值电压。 电压范围的较高值基本上等于高于第一电源电压的阈值电压。 用于定义浮动阱的电压电位的电路还包括电压发生器电路，其操作以接收控制信号并产生用于响应于控制信号设置阱的电压电位的偏置信号，偏置信号被控制在整个 电压范围。

公开(公告)号：US07170324B2

公开(公告)日：2007-01-30

申请号：US10891048

申请日：2004-07-15

申请人： Carol Ann Huber ,  John C. Kriz ,  Brian C. Lacey ,  Bernard L. Morris

发明人： Carol Ann Huber ,  John C. Kriz ,  Brian C. Lacey ,  Bernard L. Morris

IPC分类号： H03K5/12

CPC分类号： H03K17/163

摘要： A buffer design for an integrated circuit that has adjustable slew rate control, yet requires significantly less space to fabricate than does a conventional buffer with slew rate control. A new slew rate control circuit design is added to a Complementary Metal Oxide Semiconductor CMOS buffer to implement slew rate control in the buffer (e.g., selection between a high slew rate and a low slew rate). The new slew rate control circuit requires significantly less space to fabricate, and when applied to each buffer in an given integrated circuit, e.g., input/output buffers that may be placed along the periphery of the integrated circuit, the savings can be extraordinary.

摘要翻译： 用于具有可调节转换速率控制的集成电路的缓冲器设计，但与具有压摆率控制的常规缓冲器相比，制造空间要小得多。 将新的压摆率控制电路设计添加到互补金属氧化物半导体CMOS缓冲器中以在缓冲器中实现转换速率控制（例如，在高转换速率和低压摆率之间进行选择）。 新的压摆率控制电路需要明显较少的制造空间，并且当应用于给定集成电路中的每个缓冲器时，例如可以沿着集成电路的外围放置的输入/输出缓冲器，节省的成本是非同寻常的。

公开(公告)号：US08089739B2

公开(公告)日：2012-01-03

申请号：US12438460

申请日：2007-10-30

申请人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris ,  Yehuda Smooha

发明人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris ,  Yehuda Smooha

IPC分类号： H02H3/22 ,  H02H3/20 ,  H02H9/04

CPC分类号： H01L27/0266

摘要： An ESD protection circuit includes a first voltage clamp, connected between a first voltage supply node and a second voltage supply node of the circuit, and a second voltage clamp, connected between the second voltage supply node and a voltage return of the circuit. The first voltage supply node is adapted to receive a first voltage which is greater than a prescribed gate oxide reliability potential of the circuit. The second voltage supply node is operative to receive a second voltage which is less than the first voltage. The first voltage clamp is operative to clamp the first voltage on the first voltage supply node to a first value during an ESD event between the first and second voltage supply nodes, and the second voltage clamp is operative to clamp the second voltage on the second voltage supply node to a second value during an ESD event between the second voltage supply node and the voltage return.

摘要翻译： ESD保护电路包括连接在电路的第一电压供应节点和第二电压供应节点之间的第一电压钳位器，以及连接在第二电压供应节点和电路的电压回路之间的第二电压钳位。 第一电压供应节点适于接收大于电路的预定栅极氧化物可靠性电位的第一电压。 第二电压供应节点可操作以接收小于第一电压的第二电压。 第一电压钳位器用于在第一和第二电压供应节点之间的ESD事件期间将第一电压供应节点上的第一电压钳位到第一值，并且第二电压钳位器用于将第二电压钳位在第二电压 在第二电压供应节点和电压返回之间的ESD事件期间将供应节点提供给第二值。

公开(公告)号：US07432762B2

公开(公告)日：2008-10-07

申请号：US11393171

申请日：2006-03-30

申请人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris

发明人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris

IPC分类号： H03F3/45 ,  G06G7/12

CPC分类号： H03F3/45183 ,  H03F2200/513 ,  H03F2200/78 ,  H03F2203/45314 ,  H03F2203/45361 ,  H03F2203/45552 ,  H03F2203/45684

摘要： A circuit having an enhanced input signal range includes a differential amplifier operative to receive at least first and second signals and to generate a difference signal at an output thereof which is a function of the difference between the first and second signals. The differential amplifier includes an input stage having at least first and second transistors having a first threshold voltage associated therewith and being operative to receive the first and second signals, respectively, and a load including at least third and fourth transistors having a second threshold voltage associated therewith, the first threshold voltage being greater than the second threshold voltage. The circuit further includes an output stage coupled to the differential amplifier and operative to receive the difference signal and to generate an output signal of the circuit that is indicative of the difference signal and is referenced to the supply voltage of the circuit.

摘要翻译： 具有增强的输入信号范围的电路包括差分放大器，其操作以接收至少第一和第二信号，并在其输出处产生作为第一和第二信号之间的差的函数的差分信号。 差分放大器包括具有至少第一和第二晶体管的输入级，其具有与其相关联的第一阈值电压，并且可分别接收第一和第二信号，并且负载包括至少第三和第四晶体管，其具有第二阈值电压相关联 因此，第一阈值电压大于第二阈值电压。 电路还包括耦合到差分放大器的输出级并且可操作地接收差分信号并产生指示差分信号的电路的输出信号并且参考电路的电源电压。