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    Three-dimensional memory devices having a single layer channel and methods of making thereof
    3.
    发明授权
    Three-dimensional memory devices having a single layer channel and methods of making thereof 有权
    具有单层通道的三维存储器件及其制造方法

    公开(公告)号：US09530785B1

    公开(公告)日：2016-12-27

    申请号：US14804564

    申请日：2015-07-21

    申请人： SanDisk Technologies, Inc.

    发明人： Sateesh Koka ,  Zhenyu Lu ,  Wei Zhao ,  Ching-Huang Lu ,  Henry Chien ,  Yingda Dong ,  Raghuveer S. Makala ,  Somesh Peri ,  Rahul Sharangpani ,  George Matamis ,  Yuichi Ikezono ,  Hiroyuki Ogawa

    IPC分类号： H01L29/76 ,  H01L27/115

    CPC分类号： H01L27/1157 ,  H01L21/28282 ,  H01L27/0688 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582

    摘要： A memory stack structure for a three-dimensional device includes an alternating stack of insulator layers and spacer material layers. A memory opening is formed through the alternating stack. A memory material layer, a tunneling dielectric layer, and a silicon oxide liner are formed in the memory opening. A sacrificial liner is subsequently formed over the tunneling dielectric layer. The layer stack is anisotropically etched to physically expose a semiconductor surface of the substrate underneath the memory opening. The sacrificial liner may be removed prior to, or after, the anisotropic etch. The silicon oxide liner is removed after the anisotropic etch. A semiconductor channel layer can be deposited directly on the tunneling dielectric layer as a single material layer without any interface therein.

    摘要翻译： 用于三维器件的存储器堆叠结构包括交替堆叠的绝缘体层和间隔物材料层。 通过交替堆叠形成存储器开口。 在存储器开口中形成记忆材料层，隧道介电层和氧化硅衬垫。 随后在隧道电介质层上形成牺牲衬垫。 层叠堆叠被各向异性蚀刻以物理地暴露存储器开口下方的衬底的半导体表面。 可以在各向异性蚀刻之前或之后去除牺牲衬垫。 在各向异性蚀刻之后去除氧化硅衬垫。 可以将半导体沟道层直接沉积在隧道电介质层上作为单个材料层而没有任何界面。

    Memory Hole Last Boxim
    4.
    发明申请
    Memory Hole Last Boxim 有权
    记忆孔最后一次

    公开(公告)号：US20160343718A1

    公开(公告)日：2016-11-24

    申请号：US14928385

    申请日：2015-10-30

    申请人： SanDisk Technologies Inc.

    发明人： Zhenyu Lu ,  Hiro Kinoshita ,  Daxin Mao ,  Johann Alsmeier ,  Wenguang Shi ,  Yingda Dong ,  Henry Chien ,  Kensuke Yamaguchi ,  Xiaolong Hu

    IPC分类号： H01L27/115 ,  H01L23/532 ,  H01L21/768

    CPC分类号： H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

    摘要： Techniques for forming 3D memory arrays are disclosed. Memory openings are filled with a sacrificial material, such as silicon or nitride. Afterwards, a replacement technique is used to remove nitride from an ONON stack and replace it with a conductive material such as tungsten. Afterwards, memory cell films are formed in the memory openings. The conductive material serves as control gates of the memory cells. The control gate will not suffer from corner rounding. ONON shrinkage is avoided, which will prevent control gate shrinkage. Block oxide between the charge storage region and control gate may be deposited after control gate replacement, so the uniformity is good. Block oxide may be deposited after control gate replacement, so TiN adjacent to control gates can be thicker to prevent fluorine attacking the insulator between adjacent control gates. Therefore, control gate to control gate shorting is prevented.

    摘要翻译： 公开了用于形成3D存储器阵列的技术。 存储器开口填充有牺牲材料，例如硅或氮化物。 之后，使用替代技术从ONON堆叠中去除氮化物，并用诸如钨的导电材料代替它。 之后，存储单元薄膜形成在存储器开口中。 导电材料用作存储器单元的控制栅极。 控制门不会受到角落四舍五入的影响。 ONON收缩被避免，这将阻止控制门收缩。 在控制栅极更换之后，电荷存储区域和控制栅极之间的块状氧化物可能被沉积，因此均匀性良好。 在控制栅极更换之后，可以沉积块状氧化物，因此与控制栅极相邻的TiN可以更厚，以防止氟侵蚀相邻控制栅极之间的绝缘体。 因此，防止控制门短路的控制门。

    Adaptive program pulse duration based on temperature
    6.
    发明授权
    Adaptive program pulse duration based on temperature 有权
    基于温度的自适应编程脉冲持续时间

    公开(公告)号：US09437318B2

    公开(公告)日：2016-09-06

    申请号：US14522901

    申请日：2014-10-24

    申请人： SanDisk Technologies Inc.

    发明人： Yingda Dong ,  Jiahui Yuan ,  Jian Chen

    IPC分类号： G11C11/34 ,  G11C16/34 ,  G11C16/10

    CPC分类号： G11C16/3427 ,  G11C7/04 ,  G11C16/10 ,  G11C16/3431 ,  G11C16/3459

    摘要： Techniques are provided for reducing program disturb in a memory device. The techniques include compensating for a temperature in the memory device to reduce the upshift in the threshold voltage (Vth) of erased-state memory cells. A minimum allowable program pulse duration increases with temperature to account for an increase in the attenuation of a program pulse along a word line. A program pulse duration which accounts for reduced channel boosting at relatively high temperatures is reduced as the temperature increases. An optimum program pulse duration is based on the larger of these durations. The optimum program pulse duration can also be based on factors such as a measure of program disturb or a memory hole width. Program disturb can also be reduced by easing the requirements of a verify test for the highest data state.

    摘要翻译： 提供了用于减少存储器件中的程序干扰的技术。 这些技术包括补偿存储器件中的温度以减少擦除状态存储器单元的阈值电压（Vth）的升档。 最小可允许编程脉冲持续时间随着温度而增加，以增加沿着字线的编程脉冲的衰减。 在相对较高的温度下减少通道增压的程序脉冲持续时间随着温度的升高而降低。 最佳编程脉冲持续时间是基于这些持续时间中较大的一个。 最佳编程脉冲持续时间也可以基于诸如程序干扰的测量或存储器孔宽度的因素。 程序干扰也可以通过缓解对最高数据状态的验证测试的要求来降低。

    Programming memory with reduced short-term charge loss
    7.
    发明授权
    Programming memory with reduced short-term charge loss 有权

    公开(公告)号：US09437305B2

    公开(公告)日：2016-09-06

    申请号：US14925473

    申请日：2015-10-28

    申请人： SanDisk Technologies Inc.

    发明人： Ching-Huang Lu ,  Yingda Dong ,  Liang Pang ,  Tien-Chien Kuo

    IPC分类号： G11C16/10 ,  G11C16/34 ,  G11C16/04 ,  G11C11/56

    CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/3404 ,  G11C16/3459

    摘要： Techniques are provided for reducing the effects of short-term charge loss while programming charge-trapping memory cells. Short-term charge loss can result in a downshift and widening of a threshold voltage distribution. A programming operation includes a rough programming pass in which memory cells are programmed close to a final threshold voltage distribution, for each target data state. Subsequently, a negative voltage is applied to control gates of the memory cells. Subsequently, a final programming pass is performed in which the memory cells are programmed to the final threshold voltage distribution. Since the negative voltage accelerates charge loss, there is reduced charge loss after the final programming pass. The rough programming pass can use incremental step pulse programming for the lowest target data state to obtain information regarding programming speed. An initial program voltage in the final programming pass can be set based on the programming speed.

    Selective removal of charge-trapping layer for select gate transistors and dummy memory cells in 3D stacked memory
    8.
    发明授权
    Selective removal of charge-trapping layer for select gate transistors and dummy memory cells in 3D stacked memory 有权
    选择性去除3D堆叠存储器中的选择栅极晶体管和虚拟存储器单元的电荷俘获层

    公开(公告)号：US09406693B1

    公开(公告)日：2016-08-02

    申请号：US14690863

    申请日：2015-04-20

    申请人： SanDisk Technologies Inc.

    发明人： Liang Pang ,  Yingda Dong

    IPC分类号： H01L27/115 ,  H01L29/66 ,  H01L29/423 ,  H01L21/306 ,  H01L21/28 ,  H01L21/265 ,  H01L29/51 ,  H01L29/16 ,  H01L29/04

    CPC分类号： H01L27/11582 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/28282 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/32134 ,  H01L27/11563 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/04 ,  H01L29/16 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7827

    摘要： Fabrication techniques for a three-dimensional stack memory device remove the charge-trapping material from the select gate transistors and the dummy memory cells to avoid unintentional programming which increases the threshold voltage. In one approach, a stack is formed with a different sacrificial material for the a) control gate layers of the select gate transistors and the dummy memory cells and the b) control gate layers of the data memory cells. A slit is formed to allow etchants to be introduced to selectively remove the sacrificial material and then the charge-trapping material for the select gate transistors and dummy memory cells. Subsequently, an etchant is introduced to remove the sacrificial material but not the charge-trapping material for the data memory cells. In other approaches, a protective layer is provided partway in the slit, or the slit is etched in two steps, and a common sacrificial material can be used.

    摘要翻译： 用于三维堆叠存储器件的制造技术从选择栅极晶体管和虚拟存储器单元去除电荷捕获材料，以避免增加阈值电压的无意编程。 在一种方法中，堆叠形成有不同的牺牲材料，用于a）选择栅极晶体管和虚拟存储器单元的控制栅极层和b）数据存储单元的控制栅极层。 形成狭缝以允许蚀刻剂被引入以选择性地去除牺牲材料，然后选择性地去除选择栅极晶体管和虚拟存储器单元的电荷捕获材料。 随后，引入蚀刻剂以去除牺牲材料，而不是用于数据存储单元的电荷捕获材料。 在其他方法中，在狭缝中部分提供保护层，或者两个阶段蚀刻狭缝，并且可以使用共同的牺牲材料。

    Charge redistribution during erase in charge trapping memory
    9.
    发明授权
    Charge redistribution during erase in charge trapping memory 有权
    在电荷捕获存储器中的擦除期间的电荷再分配

    公开(公告)号：US09406387B2

    公开(公告)日：2016-08-02

    申请号：US14851639

    申请日：2015-09-11

    申请人： SanDisk Technologies Inc.

    发明人： Jiahui Yuan ,  Ching-Huang Lu ,  Yingda Dong

    IPC分类号： G11C16/04 ,  G11C16/14 ,  G11C16/34 ,  G11C16/16 ,  G11C11/56 ,  G11C16/26 ,  H01L27/115

    CPC分类号： G11C16/14 ,  G11C11/5635 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/344 ,  G11C16/3445 ,  G11C2211/5621 ,  H01L27/11582

    摘要： Techniques are provided to accelerate the redistribution of the holes in connection with an erase operation, so that there will be a reduced amount of redistribution of the holes after programming. As a result, short-term charge loss after programming is reduced. In one aspect, a positive control gate voltage is applied to a set of memory cells after erase and before programming. The positive control gate voltage has a relatively low amplitude and a long duration, compared to a programming voltage. The positive control gate voltage can be adjusted based on the erase depth of the memory cells and factors such as a count of program-erase cycles, a count of erase-verify iterations, sensing of a position of the lower tail, and a cross-sectional width of a vertical pillar of a memory hole.

    摘要翻译： 提供了技术来加速与擦除操作相关的孔的再分配，使得在编程之后孔将再次分配。 因此，编程后的短期电荷损失减少。 在一个方面，在擦除和编程之前，将一个正的控制栅极电压施加到一组存储器单元。 与编程电压相比，正控制栅极电压具有相对较低的幅度和长的持续时间。 可以基于存储器单元的擦除深度和诸如编程擦除周期的计数，擦除验证迭代的计数，下部尾部的位置的感测以及交叉点的位移等因素来调整正控制栅极电压。 存储孔的垂直柱的截面宽度。

    Method And Apparatus For Refresh Programming Of Memory Cells Based On Amount Of Threshold Voltage Downshift
    10.
    发明申请
    Method And Apparatus For Refresh Programming Of Memory Cells Based On Amount Of Threshold Voltage Downshift 有权
    基于门限电压降档量的存储器单元刷新编程方法与装置

    公开(公告)号：US20160211032A1

    公开(公告)日：2016-07-21

    申请号：US14600365

    申请日：2015-01-20

    申请人： SanDisk Technologies Inc.

    发明人： Liang Pang ,  Yingda Dong ,  Jian Chen

    IPC分类号： G11C16/34 ,  G11C16/26 ,  G11C16/10

    CPC分类号： G11C16/3431 ,  G11C11/5621 ,  G11C11/5671 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3459

    摘要： Techniques are provided for periodically monitoring and adjusting the threshold voltage levels of memory cells in a charge-trapping memory device. When a criterion is met, such as based on the passage of a specified time period, the memory cells are read to classify them into different subsets according to an amount of downshift in threshold voltage (Vth). Two or more subsets can be used per data state. A subset can also comprise cells which are corrected using Error Correction Code (ECC) decoding. The subsets of memory cells are refresh programmed, without being erased, in which a Vth upshift is provided in proportion to the Vth downshift. The refresh programming can use a fixed or adaptive number of program pulses per subset. Some cells will have no detectable Vth downshift or a minor amount of Vth downshift which can be ignored. These cells need not be refresh programmed.

    摘要翻译： 提供了用于周期性地监测和调整电荷俘获存储器件中的存储器单元的阈值电压电平的技术。 当满足标准时，例如基于指定时间段的过去，存储器单元被读取以根据阈值电压（Vth）的降档量将其分类成不同的子集。 每个数据状态可以使用两个或多个子集。 子集还可以包括使用纠错码（ECC）解码来校正的单元。 存储器单元的子集被刷新编程，而不被擦除，其中与Vth降档成比例地提供Vth升档。 刷新编程可以使用每个子集的固定或自适应编程脉冲数。 一些电池将没有可检测的Vth降档或少量的Vth降档，这可以被忽略。 这些单元不需要刷新编程。