Efficient smart verify method for programming 3D non-volatile memory
    2.
    发明授权
    Efficient smart verify method for programming 3D non-volatile memory 有权
    高效的智能验证方法用于编程3D非易失性存储器

    公开(公告)号:US09142302B2

    公开(公告)日:2015-09-22

    申请号:US14278374

    申请日:2014-05-15

    Abstract: In a programming operation of a 3D stacked non-volatile memory device, an initial set of memory cells on a selected word line layer, involving fewer than all memory cells on a selected word line layer, are programmed first as a test case to determine optimal conditions for programming the remaining memory cells on the selected word line layer. For example, a number of program-verify iterations or loops which are needed to program the initial set of memory cells an initial amount is determined. This loop count is then stored, e.g., within the initial set of memory cells, within the remaining memory cells, within memory cells on a remaining word line layer, or in a data register, and programming of the initial set of memory cells continues to completion. Subsequently, the loop count is retrieved and used to determine an optimal starting program voltage for programming the remaining memory cells.

    Abstract translation: 在3D堆叠非易失性存储器件的编程操作中,首先将所选字线层上的初始存储器单元集合(其涉及少于所选字线层上的所有存储器单元)作为测试用例来确定最佳值 用于编程所选字线层上的剩余存储单元的条件。 例如,确定了将初始存储器单元组编程为初始量所需的多个程序验证迭代或循环。 然后,该循环计数例如在存储单元的初始组内,剩余存储单元内,剩余字线层或数据寄存器中的存储器单元内存储,并且初始存储单元集合的编程继续 完成 随后,检索循环计数并用于确定用于编程剩余存储单元的最佳启动程序电压。

    Efficient Smart Verify Method For Programming 3D Non-Volatile Memory
    3.
    发明申请
    Efficient Smart Verify Method For Programming 3D Non-Volatile Memory 有权
    3D非易失性存储器的高效智能验证方法

    公开(公告)号:US20140226406A1

    公开(公告)日:2014-08-14

    申请号:US13940504

    申请日:2013-07-12

    Abstract: In a programming operation of a 3D stacked non-volatile memory device, an initial set of memory cells on a selected word line layer, involving fewer than all memory cells on a selected word line layer, are programmed first as a test case to determine optimal conditions for programming the remaining memory cells on the selected word line layer. For example, a number of program-verify iterations or loops which are needed to program the initial set of memory cells an initial amount is determined. This loop count is then stored, e.g., within the initial set of memory cells, within the remaining memory cells, within memory cells on a remaining word line layer, or in a data register, and programming of the initial set of memory cells continues to completion. Subsequently, the loop count is retrieved and used to determine an optimal starting program voltage for programming the remaining memory cells.

    Abstract translation: 在3D堆叠非易失性存储器件的编程操作中,首先将所选字线层上的初始存储器单元集合(其涉及少于所选字线层上的所有存储器单元)作为测试用例来确定最佳值 用于编程所选字线层上的剩余存储单元的条件。 例如,确定了将初始存储器单元组编程为初始量所需的多个程序验证迭代或循环。 然后,该循环计数例如在存储单元的初始组内,剩余存储单元内,剩余字线层或数据寄存器中的存储器单元内存储,并且初始存储器单元组的编程继续 完成 随后,检索循环计数并用于确定用于编程剩余存储单元的最佳启动程序电压。

    METHODS AND APPARATUS FOR REDUCING READ TIME FOR NONVOLATILE MEMORY DEVICES
    4.
    发明申请
    METHODS AND APPARATUS FOR REDUCING READ TIME FOR NONVOLATILE MEMORY DEVICES 审中-公开
    减少非易失性存储器件读取时间的方法和装置

    公开(公告)号:US20160189786A1

    公开(公告)日:2016-06-30

    申请号:US14926169

    申请日:2015-10-29

    Abstract: A method for operating non-volatile memory device is provided. The method includes applying a first voltage level to a word line connected to a memory cell, applying a second voltage level to the word line for a first time period, performing a read operation on the memory cell during the first time period, and discharging the word line for a second time period to a third voltage level greater than or equal to about 1V. The method also includes performing an erase word line recovery on a plurality of blocks of memory cells during the erase operation, and prior to an erase phase. The erase word line recovery substantially discharges all word lines of the plurality of blocks of memory cells.

    Abstract translation: 提供了一种用于操作非易失性存储器件的方法。 所述方法包括对连接到存储单元的字线施加第一电压电平,在第一时间段内对字线施加第二电压电平,在第一时间段内对存储器单元执行读取操作, 第二时间段的字线到大于或等于约1V的第三电压电平。 该方法还包括在擦除操作期间和在擦除阶段之前在多个存储单元块上执行擦除字线恢复。 擦除字线恢复基本上释放多个存储单元块的所有字线。

    Defective word line detection
    5.
    再颁专利
    Defective word line detection 有权
    字线检测不良

    公开(公告)号:USRE46014E1

    公开(公告)日:2016-05-24

    申请号:US14285459

    申请日:2014-05-22

    Abstract: Methods and non-volatile storage systems are provided for detecting defects in word lines. A “broken” word line defect may be detected. Information may be maintained as to which storage elements were intended to be programmed to a tracked state. Then, after programming is complete, the storage elements are read to determine which storage elements have a threshold voltage below a reference voltage level associated with the tracked state. By tracking which storage elements are in the tracked state, elements associated with other states may be filtered out such that an accurate assessment may be made as to which storage elements were under-programmed. From this information, a determination may be made whether the word line is defective. For example, if too many storage elements are under-programmed, this may indicate a broken word line.

    Abstract translation: 提供了用于检测字线中的缺陷的方法和非易失性存储系统。 可能检测到“破碎”的字线缺陷。 可以保持关于哪些存储元件被编程为跟踪状态的信息。 然后,在完成编程之后,读取存储元件以确定哪些存储元件具有低于与跟踪状态相关联的参考电压电平的阈值电压。 通过跟踪哪些存储元件处于跟踪状态,可以滤除与其他状态相关联的元件,使得可以对哪些存储元件被编程不正确进行准确的评估。 根据该信息,可以确定字线是否有缺陷。 例如,如果存储元素太多被编程不当,则这可能表示一个破损的字线。

    Efficient Smart Verify Method For Programming 3D Non-Volatile Memory

    公开(公告)号:US20140247662A1

    公开(公告)日:2014-09-04

    申请号:US14278374

    申请日:2014-05-15

    Abstract: In a programming operation of a 3D stacked non-volatile memory device, an initial set of memory cells on a selected word line layer, involving fewer than all memory cells on a selected word line layer, are programmed first as a test case to determine optimal conditions for programming the remaining memory cells on the selected word line layer. For example, a number of program-verify iterations or loops which are needed to program the initial set of memory cells an initial amount is determined. This loop count is then stored, e.g., within the initial set of memory cells, within the remaining memory cells, within memory cells on a remaining word line layer, or in a data register, and programming of the initial set of memory cells continues to completion. Subsequently, the loop count is retrieved and used to determine an optimal starting program voltage for programming the remaining memory cells.

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