公开(公告)号：US11856765B2

公开(公告)日：2023-12-26

申请号：US17317578

申请日：2021-05-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Koichi Matsuno ,  Masaaki Higashitani ,  Johann Alsmeier

IPC: H01L27/11582 ,  H10B41/27 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory opening fill structures located within an array of memory openings vertically extending through the alternating stack, and a drain-select-level isolation structure vertically extending through drain-select-level electrically conductive layers between two rows of memory opening fill structures. The drain-select-level isolation structure may comprise a low-k dielectric material or an air gap.

公开(公告)号：US20220229588A1

公开(公告)日：2022-07-21

申请号：US17149867

申请日：2021-01-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Deepanshu Dutta ,  James Kai ,  Johann Alsmeier ,  Jian Chen

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  H01L27/11582

Abstract: An integrated memory assembly comprises a memory die and a control die bonded to the memory die. The memory die comprises a three dimensional non-volatile memory structure and a first plurality of sense amplifiers. The first plurality of sense amplifiers are connected to the memory structure and are positioned on a substrate of the memory die between the memory structure and the substrate such that the memory structure is directly above the first plurality of sense amplifiers. The control die comprises a second plurality of sense amplifiers that are connected to the memory structure. The first plurality of sense amplifiers and the second plurality of sense amplifiers are configured to be used to concurrently perform memory operations.

公开(公告)号：US11222881B2

公开(公告)日：2022-01-11

申请号：US16900486

申请日：2020-06-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yanli Zhang ,  Kwang-Ho Kim ,  Johann Alsmeier

IPC: G11C16/00 ,  H01L25/18 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/48 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  G11C16/04 ,  G11C16/26 ,  G11C16/08 ,  G11C16/30 ,  H01L27/11519 ,  H01L27/11565

Abstract: A memory device includes a memory die containing memory elements, a support die containing peripheral devices and bonded to the memory die, and an electrically conductive path between two of the peripheral devices which extends at least partially through the memory die. The electrically conductive path is electrically isolated from the memory elements.

公开(公告)号：US11094704B2

公开(公告)日：2021-08-17

申请号：US16671025

申请日：2019-10-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yanli Zhang ,  Johann Alsmeier ,  Teruo Okina

IPC: H01L27/11548 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11529 ,  H01L27/11573 ,  H01L27/11575 ,  H01L21/768 ,  H01L25/065 ,  H01L23/00 ,  H01L23/48

Abstract: A method of forming a device structure includes forming a memory-level structure including a three-dimensional memory device over a front side surface of a semiconductor substrate, forming memory-side dielectric material layers over the memory-level structure, bonding a handle substrate to the memory-side dielectric material layers, thinning the semiconductor substrate while the handle substrate is attached to the memory-side dielectric material layers, forming a driver circuit including field effect transistors on a backside semiconductor surface of the semiconductor substrate after thinning the semiconductor substrate, and removing the handle substrate from the memory-side dielectric material layers.

公开(公告)号：US20210134819A1

公开(公告)日：2021-05-06

申请号：US16671025

申请日：2019-10-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yanli ZHANG ,  Johann Alsmeier ,  Teruo Okina

IPC: H01L27/11548 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11529 ,  H01L27/11573 ,  H01L27/11575 ,  H01L23/48 ,  H01L21/768 ,  H01L25/065 ,  H01L23/00

Abstract: A method of forming a device structure includes forming a memory-level structure including a three-dimensional memory device over a front side surface of a semiconductor substrate, forming memory-side dielectric material layers over the memory-level structure, bonding a handle substrate to the memory-side dielectric material layers, thinning the semiconductor substrate while the handle substrate is attached to the memory-side dielectric material layers, forming a driver circuit including field effect transistors on a backside semiconductor surface of the semiconductor substrate after thinning the semiconductor substrate, and removing the handle substrate from the memory-side dielectric material layers.

公开(公告)号：US10978482B2

公开(公告)日：2021-04-13

申请号：US16456736

申请日：2019-06-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Johann Alsmeier ,  Yanli Zhang

IPC: H01L27/1159 ,  H01L27/11597 ,  H01L29/423 ,  H01L29/78 ,  G11C11/22 ,  H01L29/66 ,  H01L21/28

Abstract: A memory cell includes a ferroelectric memory transistor, and a select gate transistor which shares a common semiconductor channel, a common source region and a common drain region with the ferroelectric memory transistor. The select gate transistor controls access between the common source region and the common semiconductor channel.

公开(公告)号：US20210028111A1

公开(公告)日：2021-01-28

申请号：US16519260

申请日：2019-07-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James KAI ,  Johann Alsmeier ,  Jixin YU

IPC: H01L23/535 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/522 ,  H01L21/768

Abstract: A vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate. Memory stack structures are formed through the vertically alternating sequence. The vertically alternating sequence is divided into alternating stacks of insulating layers and sacrificial material layers by forming backside trenches therethrough. Each neighboring pair of alternating stacks is laterally spaced apart from each other by a respective backside trench. The sacrificial material layers are replaced with multipart layers. Each multipart layer includes a respective electrically conductive layer that laterally extends continuously between a respective neighboring pair of backside trenches and at least one dielectric material plate that is a remaining portion of a sacrificial material layer, is laterally enclosed by the respective electrically conductive layer, and is laterally spaced from a most proximal one of the backside trenches by a uniform lateral offset distance.

公开(公告)号：US20200295029A1

公开(公告)日：2020-09-17

申请号：US16889030

申请日：2020-06-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jixin Yu ,  Tae-Kyung Kim ,  Johann Alsmeier ,  Yan Li ,  Jian Chen

IPC: H01L27/11578 ,  G11C5/02 ,  G11C5/06

Abstract: Three-dimensional memory devices in the form of a memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack, in which each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. Bit lines are electrically connected to an end portion of a respective one of the vertical semiconductor channels. Bump connection via structures contact a top surface of a respective one of the bit lines, in which each of the bump connection via structures has a greater lateral dimension along a lengthwise direction of the bit lines than along a widthwise direction of the bit lines. Metallic bump structures of another semiconductor die contact respective ones of the bump connection via structures to make respective electrical connections between the two dies.

公开(公告)号：US10727216B1

公开(公告)日：2020-07-28

申请号：US16409593

申请日：2019-05-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James Kai ,  Murshed Chowdhury ,  Koichi Matsuno ,  Johann Alsmeier

IPC: H01L21/76 ,  H01L25/18 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: A first wafer including a first substrate, first semiconductor devices overlying the first substrate, and first dielectric material layers overlying the first semiconductor devices is provided. A sacrificial material layer is formed over a top surface of a second wafer including a second substrate. Second semiconductor devices and second dielectric material layers are formed over a top surface of the sacrificial material layer. The second wafer is attached to the first wafer such that the second dielectric material layers face the first dielectric material layers. A plurality of voids is formed through the second substrate. The sacrificial material layer is removed by providing an etchant that etches a material of the sacrificial material layer through the plurality of voids. The substrate is detached from a bonded assembly including the first wafer, the second semiconductor devices, and the second dielectric material layers upon removal of the sacrificial material layer.

公开(公告)号：US10431313B2

公开(公告)日：2019-10-01

申请号：US15923064

申请日：2018-03-16

Applicant: SanDisk Technologies LLC

Inventor： Zhengyi Zhang ,  Yingda Dong ,  James Kai ,  Johann Alsmeier

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10 ,  G11C16/28

Abstract: A three-dimensional stacked memory device is configured to provide uniform programming speeds of different sets of memory strings formed in memory holes. In a process for removing sacrificial material from word line layers, a block oxide layer in the memory holes is etched away relatively more when the memory hole is relatively closer to an edge of the word line layers where an etchant is introduced. A thinner block oxide layer is associated with a faster programming speed. To compensate, memory strings at the edges of the word line layers are programmed together, separate from the programming of interior memory strings. A program operation can use a higher initial program voltage for programming the interior memory strings compared to the edge memory strings.