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    Three-dimensional memory device containing a pillar contact between channel and source and methods of making the same
    1.
    发明授权
    Three-dimensional memory device containing a pillar contact between channel and source and methods of making the same 有权

    公开(公告)号：US12256542B2

    公开(公告)日：2025-03-18

    申请号：US17931362

    申请日：2022-09-12

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Kyohei Nabesaka ,  Teruo Okina

    IPC: H10B41/27 ,  H10B43/20 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

    Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers, a semiconductor material layer located over the alternating stack, a dielectric spacer layer located over the semiconductor material layer, a memory opening vertically extending through the alternating stack, through the semiconductor material layer, and at least partly through the dielectric spacer layer, a memory opening fill structure located in the memory opening and including a dielectric core, a vertical semiconductor channel having a hollow portion which surrounds the dielectric core and a pillar portion which does not surround the dielectric core, and a memory film, and a source layer located over the dielectric spacer layer and contacting the pillar portion. In one embodiment, a tubular spacer laterally surrounds the pillar portion, is laterally spaced from the pillar portion by a cylindrical portion of the memory film, and contacts a cylindrical sidewall of the semiconductor material layer.

    Semiconductor die including diffusion barrier layers embedding bonding pads and methods of forming the same
    3.
    发明授权
    Semiconductor die including diffusion barrier layers embedding bonding pads and methods of forming the same 有权

    公开(公告)号：US11450624B2

    公开(公告)日：2022-09-20

    申请号：US16888188

    申请日：2020-05-29

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Noriaki Oda ,  Teruo Okina

    IPC: H01L23/48 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00 ,  H01L25/065

    Abstract: Semiconductor devices can be formed over a semiconductor substrate, and interconnect-level dielectric material layers embedding metal interconnect structures can be formed thereupon. In one embodiment, a pad-connection-via-level dielectric material layer, a proximal dielectric diffusion barrier layer, and a pad-level dielectric material layer can be formed. Bonding pads surrounded by dielectric diffusion barrier portions can be formed in the pad-level dielectric material layer. In another embodiment, a layer stack of a proximal dielectric diffusion barrier layer and a pad-and-via-level dielectric material layer can be formed. Integrated pad and via cavities can be formed through the pad-and-via-level dielectric material layer, and can be filled with bonding pads containing dielectric diffusion barrier portions and integrated pad and via structures.

    Bonded three-dimensional memory devices and methods of making the same by replacing carrier substrate with source layer
    4.
    发明授权
    Bonded three-dimensional memory devices and methods of making the same by replacing carrier substrate with source layer 有权

    公开(公告)号：US11201107B2

    公开(公告)日：2021-12-14

    申请号：US16829591

    申请日：2020-03-25

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Teruo Okina ,  Akio Nishida ,  James Kai

    IPC: H01L23/48 ,  H01L25/065 ,  H01L21/768 ,  H01L23/00 ,  H01L27/11582

    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a carrier substrate. Memory stack structures vertically extend through the alternating stack. Each memory stack structure includes a respective vertical semiconductor channel and a respective memory film. A pass-through via structure vertically extends through a dielectric material portion that is adjacent to the alternating stack. The memory die can be bonded to a logic die containing peripheral circuitry for supporting operations of memory cells within the memory die. A distal end of each of the vertical semiconductor channels is physically exposed by removing the carrier substrate. A source layer is formed directly on the distal end each of the vertical semiconductor channels. A backside bonding pad or bonding wire is formed to be electrically connected to the pass-through via structure.

    Semiconductor die containing dummy metallic pads and methods of forming the same
    7.
    发明授权
    Semiconductor die containing dummy metallic pads and methods of forming the same 有权

    公开(公告)号：US11322466B2

    公开(公告)日：2022-05-03

    申请号：US16879146

    申请日：2020-05-20

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Teruo Okina

    IPC: H01L23/522 ,  H01L23/00 ,  H01L23/58 ,  H01L25/18 ,  H01L25/00 ,  H01L23/528

    Abstract: A first semiconductor die includes first semiconductor devices located over a first substrate, first interconnect-level dielectric layers embedding first metal interconnect structures and located over the first semiconductor devices, a first pad-level dielectric layer embedding first bonding pads and located over the first interconnect-level dielectric layers, and first edge seal structures laterally surrounding the first semiconductor devices. Each of the first edge seal structures vertically extends from the first substrate to a distal surface of the first pad-level dielectric layer, and includes a respective first pad-level ring structure that continuously extends around the first semiconductor devices. At least one row of first dummy metal pads is embedded in the first pad-level dielectric layer between a respective pair of first edge seal structures. Second pad-level ring structures embedded in a second semiconductor die can be bonded to the rows of first dummy metal pads.

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