公开(公告)号：US20120273782A1

公开(公告)日：2012-11-01

申请号：US13118201

申请日：2011-05-27

申请人： Sandeep Kumar GOEL ,  Mill-Jer WANG ,  Chung-Sheng YUAN ,  Tom CHEN ,  Chao-Yang YEH ,  Chin-Chou LIU ,  Yun-Han LEE

发明人： Sandeep Kumar GOEL ,  Mill-Jer WANG ,  Chung-Sheng YUAN ,  Tom CHEN ,  Chao-Yang YEH ,  Chin-Chou LIU ,  Yun-Han LEE

IPC分类号： H01L23/48 ,  G06F17/50

CPC分类号： H01L22/32 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/00

摘要： An interposer of a package system includes a first probe pad disposed adjacent to a first surface of the interposer. A second probe pad is disposed adjacent to the first surface of the interposer. A first bump of a first dimension is disposed adjacent to the first surface of the interposer. The first bump is electrically coupled with the first probe pad. A second bump of the first dimension is disposed adjacent to the first surface of the interposer. The second bump is electrically coupled with the second probe pad. The second bump is electrically coupled with the first bump through a redistribution layer (RDL) of the interposer.

摘要翻译： 封装系统的插入件包括邻近插入件的第一表面设置的第一探针焊盘。 第二探针焊盘设置成与插入件的第一表面相邻。 第一尺寸的第一凸起设置成与插入件的第一表面相邻。 第一凸块与第一探针垫电耦合。 第一尺寸的第二凸起设置成与插入件的第一表面相邻。 第二凸起与第二探针垫电耦合。 第二凸起通过中介层的再分配层（RDL）与第一凸块电耦合。

公开(公告)号：US20130147505A1

公开(公告)日：2013-06-13

申请号：US13313228

申请日：2011-12-07

申请人： Mill-Jer WANG ,  Ching-Fang CHEN ,  Sandeep Kumar GOEL ,  Chung-Sheng YUAN ,  Chao-Yang YEH ,  Chin-Chou LIU ,  Yun-Han LEE ,  Hung-Chih LIN

发明人： Mill-Jer WANG ,  Ching-Fang CHEN ,  Sandeep Kumar GOEL ,  Chung-Sheng YUAN ,  Chao-Yang YEH ,  Chin-Chou LIU ,  Yun-Han LEE ,  Hung-Chih LIN

IPC分类号： G01R1/067

CPC分类号： G01R1/07342 ,  G01R1/07378 ,  H01L2224/16225

摘要： A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.

摘要翻译： 用于晶圆级测试的半导体IC封装器件（DUT）的测试探针结构。 该结构包括衬底，通过衬底通孔，形成在用于接合探针卡的衬底的第一表面上的凸块阵列，以及在衬底的第二表面上的至少一个探测单元。 探测单元包括形成在衬底的一个表面上的导电探针焊盘和与衬垫相互连接的至少一个微型凹坑。 焊盘通过通孔电连接到凸块阵列。 一些实施例包括与衬垫相关联的多个微胶囊，其被配置成接合DUT上的微胶囊的匹配阵列。 在一些实施例中，可以通过将来自探针卡的测试信号通过凸块和微型阵列来探测DUT，而不直接探测DUT微胶囊。

公开(公告)号：US20130127441A1

公开(公告)日：2013-05-23

申请号：US13299445

申请日：2011-11-18

申请人： Nan-Hsin TSENG ,  Chin-Chou LIU ,  Saurabh GUPTA ,  Ji-Jan CHEN ,  Chi Wei HU

发明人： Nan-Hsin TSENG ,  Chin-Chou LIU ,  Saurabh GUPTA ,  Ji-Jan CHEN ,  Chi Wei HU

IPC分类号： G01R19/00

CPC分类号： G01R19/16552 ,  G01R19/2503 ,  G01R31/31924

摘要： Test points on an integrated circuit chip, especially points subject to IR voltage drop along power supply rails, are coupled to comparators controlled by an automatic test controller, all included on the chip. Each test point can have one or more comparators and one or more reference voltages over a testing range. A change of state at a comparator sets a latch that is read and reset by the on-chip automatic test controller during test intervals. The automatic test controller can coordinate with external automatic test equipment that applies stimulus signals to the chip during testing. The greatest voltage drop during a test interval is determined from the latched output of the switched comparator coupled to the lowest reference voltage. The setting and resetting of the latch can be gated through a selectable delay so as to discriminate for excursions that persist for a longer or shorter time.

摘要翻译： 集成电路芯片上的测试点，特别是沿着电源轨的IR电压降的点被耦合到由芯片上所有的自动测试控制器控制的比较器。 每个测试点可以在测试范围内具有一个或多个比较器和一个或多个参考电压。 比较器状态的改变设置在测试间隔期间由片上自动测试控制器读取和复位的锁存器。 自动测试控制器可以在测试期间与外部自动测试设备进行协调，并将激励信号施加到芯片。 测试间隔期间的最大电压降由耦合到最低参考电压的开关比较器的锁存输出确定。 闩锁的设置和复位可以通过可选择的延迟来选通，以便区分持续更长或更短时间的偏移。

公开(公告)号：US20130193981A1

公开(公告)日：2013-08-01

申请号：US13362576

申请日：2012-01-31

申请人： Chih-Chia CHEN ,  Kuan-Yu LIN ,  Chin-Chou LIU

发明人： Chih-Chia CHEN ,  Kuan-Yu LIN ,  Chin-Chou LIU

IPC分类号： G01R31/02 ,  H03K5/22

CPC分类号： G01R19/16552 ,  G01R31/2856 ,  G01R31/318513 ,  H03K5/24

摘要： A circuit including a first switch receiving an input reference voltage, a second switch receiving an input testing voltage, the first switch and the second switch are electrically connected in parallel. The circuit further includes a first capacitor electrically connected in series with the first switch and the second switch. The circuit further includes a feedback stage comprising a feedback inverter electrically connected in parallel with a feedback switch, where the feedback stage is electrically connected in series with the first capacitor. The circuit further includes a first inverter electrically connected in series to the feedback stage, and a third switch electrically connected in series with the first inverter. The circuit further includes a second inverter electrically connected in parallel to a third inverter, the second inverter and the third inverter are electrically connected in series to the third switch, and the third inverter outputs a first output signal.

摘要翻译： 包括接收输入参考电压的第一开关，接收输入测试电压的第二开关，第一开关和第二开关的电路并联电连接。 电路还包括与第一开关和第二开关串联电连接的第一电容器。 电路还包括反馈级，其包括与反馈开关并联电连接的反馈反相器，其中反馈级与第一电容器串联电连接。 电路还包括与反馈级串联电连接的第一反相器和与第一反相器串联电连接的第三开关。 电路还包括与第三反相器并联电连接的第二反相器，第二反相器和第三反相器与第三开关串联电连接，并且第三反相器输出第一输出信号。

公开(公告)号：US20130257564A1

公开(公告)日：2013-10-03

申请号：US13437047

申请日：2012-04-02

申请人： Bo-Jr HUANG ,  Yi-Wei CHEN ,  Kuan-Yu LIN ,  Chin-Chou LIU

发明人： Bo-Jr HUANG ,  Yi-Wei CHEN ,  Kuan-Yu LIN ,  Chin-Chou LIU

IPC分类号： H03H7/01

CPC分类号： H01L23/49822 ,  H01F2017/0086 ,  H01L23/147 ,  H01L23/49827 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/13091 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/16172 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H03H7/0115 ,  H03H2001/0085 ,  H01L2924/014 ,  H01L2924/00

摘要： An interposer element in a multidimensional integrated circuit with stacked elements has one or more conductors, especially power supply lines, coupled through decoupling networks defining low impedance shunts for high frequency signals to ground. The interposer has successive tiers including silicon, metal and dielectric deposition layers. The decoupling network for a conductor has at least one and preferably two reactive transmission lines. A transmission line has an inductor in series with the conductor and parallel capacitances at the inductor terminals. The inductors are formed by traces in spaced metal deposition layers forming coil windings and through vias connecting between layers to permit conductor crossovers. The capacitances are formed by MOScaps in the interposer layers. An embodiment has serially coupled coils with capacitances at the input, output and junction between the coils, wherein the coils are magnetically coupled to form a transformer.

摘要翻译： 具有堆叠元件的多维集成电路中的插入元件具有一个或多个导体，特别是电源线，其通过去耦网络耦合，所述解耦网络限定用于将高频信号接地的低阻抗分流。 插入器具有连续的层，包括硅，金属和介电沉积层。 用于导体的去耦网络具有至少一个且优选两个无功传输线。 传输线具有与导体串联的电感器和电感器端子处的并联电容。 电感器由形成线圈绕组的间隔开的金属沉积层中的迹线形成，并且通过在层之间连接的通孔以允许导体交叉。 电容由插入层中的MOS框形成。 实施例具有在线圈之间的输入，输出和结点处具有电容的串联耦合线圈，其中线圈被磁耦合以形成变压器。

公开(公告)号：US20110273967A1

公开(公告)日：2011-11-10

申请号：US13110735

申请日：2011-05-18

申请人： Nan-Hsin TSENG ,  Chin-Chou LIU ,  Saurabh GUPTA

发明人： Nan-Hsin TSENG ,  Chin-Chou LIU ,  Saurabh GUPTA

IPC分类号： G04F10/00

CPC分类号： G04F10/005

摘要： A method for high-resolution timing measurement includes a first oscillator generating a first clock with a first frequency. A second oscillator generates a second clock with a second frequency. A delay pulse generator generates a delayed pulse from the second clock. An oscillator tuner controls the second frequency to be as close as possible to the first frequency without being the same as the first frequency. A sampling module samples the delayed pulse at the first frequency. A counter generates a digital counter value by counting a number of samples made by the sampling module.

摘要翻译： 用于高分辨率定时测量的方法包括产生具有第一频率的第一时钟的第一振荡器。 第二振荡器产生具有第二频率的第二时钟。 延迟脉冲发生器从第二时钟产生延迟的脉冲。 振荡器调谐器控制第二频率尽可能接近于第一频率，而不与第一频率相同。 采样模块以第一个频率采样延迟脉冲。 计数器通过对由采样模块进行的采样数进行计数来产生数字计数器值。

公开(公告)号：US20110038451A1

公开(公告)日：2011-02-17

申请号：US12757396

申请日：2010-04-09

申请人： Nan-Hsin TSENG ,  Chin-Chou LIU ,  Saurabh GUPTA

发明人： Nan-Hsin TSENG ,  Chin-Chou LIU ,  Saurabh GUPTA

IPC分类号： G04F10/04

CPC分类号： G04F10/005

摘要： An integrated circuit for high-resolution timing measurement includes a delay pulse generator, the first oscillator to generate the first clock with the first frequency, the second oscillator to generate the second clock with the second frequency, an oscillator tuner, a sampling module, a counter, wherein the delay pulse generator generated a delayed pulse from the second clock, the oscillator tuner controls the second frequency to be as close as possible to the first frequency without being the same as the second frequency, the sampling module samples the delayed pulse at the first frequency, the counter generates a digital counter value by counting a number of sampling by the sampling module, and a time width of the delayed pulse can be calculated by the digital counter value. The second oscillator can be a tunable ring oscillator with one or more coarse tune stages and one or more fine-tune stages.

摘要翻译： 用于高分辨率定时测量的集成电路包括延迟脉冲发生器，第一振荡器，用于产生具有第一频率的第一时钟，第二振荡器产生具有第二频率的第二时钟，振荡器调谐器，采样模块， 计数器，其中所述延迟脉冲发生器从所述第二时钟产生延迟脉冲，所述振荡器调谐器控制所述第二频率尽可能接近所述第一频率而不与所述第二频率相同，所述采样模块将所述延迟脉冲采样 第一频率，计数器通过对采样模块进行采样次数的计数来产生数字计数器值，并且可以通过数字计数器值计算延迟脉冲的时间宽度。 第二振荡器可以是具有一个或多个粗调级和一个或多个微调级的可调谐环形振荡器。