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    TEST PROBING STRUCTURE
    2.
    发明申请
    TEST PROBING STRUCTURE 有权
    测试探测结构

    公开(公告)号：US20130147505A1

    公开(公告)日：2013-06-13

    申请号：US13313228

    申请日：2011-12-07

    申请人： Mill-Jer WANG ,  Ching-Fang CHEN ,  Sandeep Kumar GOEL ,  Chung-Sheng YUAN ,  Chao-Yang YEH ,  Chin-Chou LIU ,  Yun-Han LEE ,  Hung-Chih LIN

    发明人： Mill-Jer WANG ,  Ching-Fang CHEN ,  Sandeep Kumar GOEL ,  Chung-Sheng YUAN ,  Chao-Yang YEH ,  Chin-Chou LIU ,  Yun-Han LEE ,  Hung-Chih LIN

    IPC分类号： G01R1/067

    CPC分类号： G01R1/07342 ,  G01R1/07378 ,  H01L2224/16225

    摘要： A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.

    摘要翻译： 用于晶圆级测试的半导体IC封装器件（DUT）的测试探针结构。 该结构包括衬底，通过衬底通孔，形成在用于接合探针卡的衬底的第一表面上的凸块阵列，以及在衬底的第二表面上的至少一个探测单元。 探测单元包括形成在衬底的一个表面上的导电探针焊盘和与衬垫相互连接的至少一个微型凹坑。 焊盘通过通孔电连接到凸块阵列。 一些实施例包括与衬垫相关联的多个微胶囊，其被配置成接合DUT上的微胶囊的匹配阵列。 在一些实施例中，可以通过将来自探针卡的测试信号通过凸块和微型阵列来探测DUT，而不直接探测DUT微胶囊。

    METHOD OF GENERATING AN INTELLECTUAL PROPERTY BLOCK DESIGN KIT, METHOD OF GENERATING AN INTEGRATED CIRCUIT DESIGN, AND SIMULATION SYSTEM FOR THE INTEGRATED CIRCUIT DESIGN
    3.
    发明申请
    METHOD OF GENERATING AN INTELLECTUAL PROPERTY BLOCK DESIGN KIT, METHOD OF GENERATING AN INTEGRATED CIRCUIT DESIGN, AND SIMULATION SYSTEM FOR THE INTEGRATED CIRCUIT DESIGN 有权
    产生知识产权块设计套件的方法，集成电路设计的生成方法以及集成电路设计的仿真系统

    公开(公告)号：US20120131523A1

    公开(公告)日：2012-05-24

    申请号：US12950371

    申请日：2010-11-19

    申请人： Lee-Chung LU ,  Yun-Han LEE ,  Wei-Li CHEN ,  Tan-Li CHOU ,  Kheng-Guan TAN ,  Shi-Hung WANG

    发明人： Lee-Chung LU ,  Yun-Han LEE ,  Wei-Li CHEN ,  Tan-Li CHOU ,  Kheng-Guan TAN ,  Shi-Hung WANG

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G06F17/5022 ,  G06F2217/02 ,  G06F2217/66

    摘要： The present application discloses a method of generating an intellectual property (IP) block design kit including an IP block circuit design and a system-level characteristics table for manufacturing an integrated circuit. According at least one embodiment, the IP block circuit design is generated. The IP block circuit design is simulated based on predetermined configuration sets, and each configuration set has manufacturing options and/or operating conditions. A plurality of system-level models for the predetermined configuration sets are generated based on the simulation of the IP block circuit design. The system-level characteristics table is generated by arranging the predetermined configuration sets and the system-level models in compliance with a system-level characteristics table template of a system-level characteristics modeling device. Then the IP block circuit design and the system-level characteristics table are stored as the IP block design kit.

    摘要翻译： 本申请公开了一种生成包括IP块电路设计和用于制造集成电路的系统级特性表的知识产权（IP）块设计套件的方法。 根据至少一个实施例，产生IP块电路设计。 IP块电路设计基于预定的配置集进行仿真，每个配置集都具有制造选项和/或操作条件。 基于IP块电​​路设计的仿真，生成用于预定配置集的多个系统级模型。 通过根据系统级特征建模设备的系统级特征表模板布置预定配置集和系统级模型来生成系统级特征表。 然后将IP块电路设计和系统级特性表存储为IP块设计工具包。

    RETENTION FLIP-FLOP
    4.
    发明申请
    RETENTION FLIP-FLOP 有权
    保留FLIP-FLOP

    公开(公告)号：US20110248759A1

    公开(公告)日：2011-10-13

    申请号：US12758096

    申请日：2010-04-12

    申请人： Shyh-An CHI ,  Shiue Tsong SHEN ,  Jyy Anne LEE ,  Yun-Han LEE

    发明人： Shyh-An CHI ,  Shiue Tsong SHEN ,  Jyy Anne LEE ,  Yun-Han LEE

    IPC分类号： H03K3/289

    CPC分类号： H03K3/356156 ,  H03K3/356008 ,  H03K3/35625

    摘要： A master-slave retention flip-flop includes a master latch adapted to latch an input data signal and to output a latched master latch data signal based on an input clock signal, a slave latch coupled to an output of the master latch and adapted to output a latched slave latch data signal based on the input clock signal, and a retention latch embedded within one of the master and slave latches adapted to preserve data in a power down mode based on a power down control signal.

    摘要翻译： 主从保持触发器包括主锁存器，其适于锁存输入数据信号并且基于输入时钟信号输出锁存的主锁存数据信号，从锁存器耦合到主锁存器的输出并且适于输出 基于输入时钟信号的锁存的从锁存数据信号，以及嵌入在主锁存器和从锁存器之一内的保持锁存器，其适于基于掉电控制信号在掉电模式下保留数据。

    SUBSTRATE BIAS CONTROL CIRCUIT FOR SYSTEM ON CHIP
    6.
    发明申请
    SUBSTRATE BIAS CONTROL CIRCUIT FOR SYSTEM ON CHIP 有权
    用于芯片系统的基板偏置控制电路

    公开(公告)号：US20110095811A1

    公开(公告)日：2011-04-28

    申请号：US12793884

    申请日：2010-06-04

    申请人： Shyh-An CHI ,  Shiue Tsong SHEN ,  Jyy Anne LEE ,  Yun-Han LEE

    发明人： Shyh-An CHI ,  Shiue Tsong SHEN ,  Jyy Anne LEE ,  Yun-Han LEE

    IPC分类号： H01L37/00

    CPC分类号： G05F3/205 ,  H03K19/00384

    摘要： A substrate bias control circuit includes a process voltage temperature (PVT) effect transducer that responds to a PVT effect. A PVT effect quantifier is coupled to the PVT effect transducer. The PVT effect quantifier quantifies the PVT effect to provide an output. The PVT effect quantifier includes at least one counter and a period generator. The period generator provides a time period for the counter. A bias controller that is coupled to PVT effect quantifier is configured to receive the output of the PVT effect quantifier. The bias controller is configured to provide a bias voltage. The bias controller includes a bias voltage comparator.

    摘要翻译： 衬底偏置控制电路包括响应PVT效应的工艺电压温度（PVT）效应传感器。 PVT效应量化器耦合到PVT效应传感器。 PVT效应量词量化PVT效应以提供输出。 PVT效应量化器包括至少一个计数器和周期发生器。 周期发生器为计数器提供一个时间段。 耦合到PVT效应量化器的偏置控制器被配置为接收PVT效应量化器的输出。 偏置控制器被配置为提供偏置电压。 偏置控制器包括偏置电压比较器。