公开(公告)号：US5257232A

公开(公告)日：1993-10-26

申请号：US847769

申请日：1992-03-05

申请人： Sang H. Dhong ,  Koji Kitamura ,  Toshiaki Kirihata ,  Toshio Sunaga

发明人： Sang H. Dhong ,  Koji Kitamura ,  Toshiaki Kirihata ,  Toshio Sunaga

IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C11/407 ,  G11C11/4091 ,  G11C13/00

CPC分类号： G11C11/4091 ,  G11C7/065

摘要： A sensing circuit for dynamic random access memory is disclosed including a pair of bitlines precharged to a first voltage before sensing. A sense amplifier circuit is provided having one node thereof being connected to an external power supply via a switching means including pulsed sense clocks. Control means is provided and is connected to the switching means for controlling the switching means such that the voltage of the power supply is coupled to the node of the sense amplifier for activation for a predetermined period of time, thereby limiting the swing for the high-going bitline to a second voltage lower than said power supply voltage and higher than the first voltage. The reduced bit-line swings are achieved by means of the pulsed sense clocks and the pulse widths for sense clocks are determined by means of a reference bitlines connected to the control means.

公开(公告)号：US5339274A

公开(公告)日：1994-08-16

申请号：US969644

申请日：1992-10-30

申请人： Sang H. Dhong ,  Toshiaki Kirihata ,  Hyun J. Shin ,  Toshio Sunaga ,  Yoichi Taira ,  Lewis M. Terman

发明人： Sang H. Dhong ,  Toshiaki Kirihata ,  Hyun J. Shin ,  Toshio Sunaga ,  Yoichi Taira ,  Lewis M. Terman

IPC分类号： G11C11/409 ,  G11C11/407 ,  G11C11/4094 ,  G11C7/00

CPC分类号： G11C11/4094

摘要： A sensing technique uses a variable precharge voltage sensing with a single bitline swing in a DRAM cell or array of DRAM cells so that the power dissipation is reduced. The bitline precharge voltage varies from one RAS cycle to the next RAS cycle depending upon the level of the data in the accessed cells. Such an arrangement eliminates the need for a reference voltage generator since the precharge voltage is not the same voltage for each RAS cycle.

摘要翻译： 感测技术在DRAM单元或DRAM单元阵列中使用单个位线摆动的可变预充电电压感测，从而降低功耗。 位线预充电电压根据所访问的单元中的数据的电平而从一个RAS周期到下一个RAS周期变化。 这种布置消除了对参考电压发生器的需要，因为对于每个RAS周期，预充电电压不是相同的电压。

公开(公告)号：US5483179A

公开(公告)日：1996-01-09

申请号：US230265

申请日：1994-04-20

申请人： Sang H. Dhong ,  Toshiaki Kirihata ,  Matthew R. Wordeman

发明人： Sang H. Dhong ,  Toshiaki Kirihata ,  Matthew R. Wordeman

IPC分类号： H03K17/687 ,  G05F3/24 ,  H03K19/0175 ,  H01L25/00

CPC分类号： G05F3/24

摘要： A device for controlling the voltage across an NMOS pull-up transistor including a source node which may be exposed to a variable voltage. The device further includes a gate node which may be exposed to a variable voltage. A control portion regulates the voltage applied to the gate node, wherein a differential in voltage between the source node and the gate node is limited to a desired level.

摘要翻译： 用于控制跨越NMOS上拉晶体管的电压的装置，其包括可能暴露于可变电压的源节点。 该器件还包括可以暴露于可变电压的栅极节点。 控制部分调节施加到栅极节点的电压，其中源节点和栅极节点之间的电压差被限制到期望的电平。

公开(公告)号：US5541887A

公开(公告)日：1996-07-30

申请号：US375025

申请日：1995-01-19

申请人： Sang H. Dhong ,  Wei Hwang ,  Toshiaki Kirihata

发明人： Sang H. Dhong ,  Wei Hwang ,  Toshiaki Kirihata

IPC分类号： G11C8/16 ,  G11C29/50 ,  G11C7/00

CPC分类号： G11C29/50 ,  G11C8/16

摘要： Sequentially terminated write enable pulses applied to respective input ports of a multi-port memory cell is effective to establish a priority among those input ports and provide unconditionally unambiguous writing to a memory cell when write operations are concurrently attempted at two or more ports of that cell, as may be encountered during rigorous testing procedures. Memory structure, particularly that of the input port circuits, is simplified and operational speed is enhanced since signal propagation through a comparator or logic circuit is avoided. Time required for testing of large memory arrays is also significantly reduced.

摘要翻译： 施加到多端口存储器单元的相应输入端口的顺序终止写入使能脉冲对于在这些输入端口之间建立优先级是有效的，并且当在该单元的两个或更多个端口同时尝试写入操作时，向存储器单元提供无条件地明确的写入 ，如在严格的测试程序中可能遇到的。 存储器结构，特别是输入端口电路的存储器结构被简化，并且由于避免了通过比较器或逻辑电路的信号传播，因此提高了操作速度。 大型存储器阵列测试所需的时间也大大减少。

公开(公告)号：US07404113B2

公开(公告)日：2008-07-22

申请号：US11031138

申请日：2005-01-07

申请人： Louis L. Hsu ,  Gregory J. Fredeman ,  Rajiv V. Joshi ,  Toshiaki Kirihata

发明人： Louis L. Hsu ,  Gregory J. Fredeman ,  Rajiv V. Joshi ,  Toshiaki Kirihata

IPC分类号： G11C29/00

CPC分类号： G11C29/808

摘要： A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size.

摘要翻译： 提供了一种用于替换具有多个存储体的存储器阵列的有缺陷的字线的行冗余系统。 行冗余系统包括存储与存储器阵列的故障字线相对应的至少一个故障地址的远程熔丝架; 用于存储对应于所述存储器阵列的至少一个组的行熔丝信息的行熔丝阵列; 以及复制逻辑模块，用于将存储在所述远程保险丝盒中的至少一个故障地址复制到所述行保险丝阵列中; 复制逻辑模块被编程为根据可选择的修复字段大小将至少一个故障地址复制到存储在对应于预定数量的存储体的行熔丝阵列中的行熔丝信息中。

公开(公告)号：US07146471B2

公开(公告)日：2006-12-05

申请号：US10748333

申请日：2003-12-31

申请人： Toshiaki Kirihata ,  Gerhard Mueller ,  Wing K. Luk

发明人： Toshiaki Kirihata ,  Gerhard Mueller ,  Wing K. Luk

IPC分类号： G06F12/02

CPC分类号： G06F13/1694 ,  Y02D10/14

摘要： A memory system that employs simultaneous activation of at least two dissimilar memory arrays, during a data manipulation, such as read or write operations is disclosed. An exemplary embodiment includes a memory system containing a plurality of arrays, each in communication with a common controller, wherein the arrays are activated by different supply voltage (Vdd). When a processor sends a command to retrieve or write data to the memory system, two or more arrays are addressed to supply the required data. By proper partitioning of the data between dissimilar arrays, the efficiency of data reading is improved.

摘要翻译： 公开了一种在诸如读取或写入操作的数据操作期间同时激活至少两个不同的存储器阵列的存储器系统。 示例性实施例包括包含多个阵列的存储器系统，每个阵列与公共控制器通信，其中阵列由不同的电源电压（Vdd）激活。 当处理器发送命令以检索或写入数据到存储器系统时，寻址两个或更多个阵列以提供所需的数据。 通过在不同阵列之间适当分割数据，数据读取的效率得到提高。

公开(公告)号：US07085180B2

公开(公告)日：2006-08-01

申请号：US10777596

申请日：2004-02-12

申请人： Gregory J. Fredeman ,  Mark D. Jacunski ,  Toshiaki Kirihata ,  Matthew R. Wordeman

发明人： Gregory J. Fredeman ,  Mark D. Jacunski ,  Toshiaki Kirihata ,  Matthew R. Wordeman

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/4401 ,  G11C29/40 ,  G11C29/44 ,  G11C29/808 ,  G11C2029/0401 ,  G11C2029/2602

摘要： A method for allocating redundancies during a multi-bank operation in a memory device which includes two or more redundancy domains is described. The method includes steps of enabling a pass/fail bit detection to activate a given bank. The pass/fail bit detection is prompted only for a selected domain and is disabled when it addresses other domains. By altering the domain selection, it is possible to enable a redundancy allocation for any domain regardless of the multi-bank operation. The method may preferably be realized by using a dynamic exclusive-OR logic with true and complement expected data pairs. When combined with simple pointer logic, the selection of domains may be generated internally, simplifying the built in self-test and other test control protocols, while at the same time tracking those that fail.

摘要翻译： 描述了在包括两个或更多个冗余域的存储器设备中在多存储体操作期间分配冗余的方法。 该方法包括启用通过/故障位检测来激活给定的存储体的步骤。 通过/失败位检测仅对选定的域提示，并且在寻址其他域时被禁用。 通过改变域选择，无论多行操作如何，都可以为任何域启用冗余分配。 该方法可以优选地通过使用具有真实和补充预期数据对的动态异或逻辑来实现。 当结合简单的指针逻辑时，可以内部生成域的选择，简化内置的自检和其他测试控制协议，同时跟踪失败的那些。

公开(公告)号：US20050226083A1

公开(公告)日：2005-10-13

申请号：US11160220

申请日：2005-06-14

申请人： Brian Ji ,  Chorng-Lii Hwang ,  Toshiaki Kirihata ,  Seiji Munetoh

发明人： Brian Ji ,  Chorng-Lii Hwang ,  Toshiaki Kirihata ,  Seiji Munetoh

IPC分类号： G06F12/00 ,  G06F12/08 ,  G11C7/10 ,  G11C8/00 ,  G11C8/12 ,  G11C11/401 ,  G11C11/4093

CPC分类号： G11C8/12 ,  G06F12/0804 ,  G06F12/0893 ,  G06F12/0897 ,  G06F2212/3042 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/106 ,  G11C11/4093 ,  G11C2207/2245

摘要： A memory storage system includes a plurality of memory storage banks and a cache in communication therewith. Both the plurality of memory storage banks and the cache further include destructive read memory storage elements configured for delayed write back scheduling thereto.

摘要翻译： 存储器存储系统包括多个存储器存储体和与之通信的高速缓冲存储器。 多个存储器存储体和高速缓存还包括配置用于对其进行延迟回写调度的破坏性读取存储器存储元件。

公开(公告)号：US06845059B1

公开(公告)日：2005-01-18

申请号：US10604109

申请日：2003-06-26

申请人： Matthew R. Wordeman ,  John E. Barth ,  Toshiaki Kirihata

发明人： Matthew R. Wordeman ,  John E. Barth ,  Toshiaki Kirihata

IPC分类号： G11C7/10 ,  G11C8/16 ,  G11C11/406 ,  G11C11/4096 ,  G11C8/00

CPC分类号： G11C8/16 ,  G11C7/106 ,  G11C7/1087 ,  G11C11/40603 ,  G11C11/40615

摘要： A memory architecture that utilizes single-ended dual-port destructive write memory cells and a local write-back buffer is described. Each cell has separate read and write ports that make it possible to read-out data from cells on one wordline in the array, and subsequently write-back to those cells while simultaneously reading-out the cell on another wordline in the array. By implementing an array of sense amplifiers such that one amplifier is coupled to each read bitline, and a latch receiving the result of the sensed data and delivering this data to the write data lines, it is possible to ‘pipeline’ the read-out and write-back phases of the read cycle. This allows for a write-back phase from one cycle to occur simultaneously with the read-out phase of another cycle. By extending the operation of the latch to accept data either from the sense amplifier, or from the memory data inputs, modified by the column address and masking bits, it is also possible to pipeline the read-out and the modify-write-back phases of a write cycle, allowing them to occur simultaneously. The architecture preferably employs a nondestructive read memory cell such as 2T or 3T gain cells, achieving an SRAM-like cycle and access times with a smaller and more SER immune memory cell.

摘要翻译： 描述了利用单端双端口破坏性写存储器单元和本地回写缓冲器的存储架构。 每个单元都具有单独的读取和写入端口，可以从阵列中的一个字线上的单元读出数据，随后将其写回到这些单元格，同时读出数组中另一个字线上的单元格。 通过实现读出放大器的阵列，使得一个放大器耦合到每个读取位线，以及一个接收感测数据的结果并将该数据传送到写入数据线的锁存器，可以“管理”读出和 读周期的回写阶段。 这允许来自一个周期的回写阶段与另一个周期的读出阶段同时发生。 通过扩展锁存器的操作以接受来自读出放大器或由存储器数据输入的数据，由列地址和掩码位修改，还可以管理读出和修改回写阶段 的写周期，允许它们同时发生。 该架构优选采用非破坏性读取存储器单元，例如2T或3T增益单元，通过较小和更多的SER免疫存储单元实现SRAM类周期和访问时间。

公开(公告)号：US06674673B1

公开(公告)日：2004-01-06

申请号：US10064867

申请日：2002-08-26

申请人： Louis Lu-Chen Hsu ,  Gregory Fredeman ,  Chorng-Lii Hwang ,  Toshiaki Kirihata ,  Dale E. Pontius

发明人： Louis Lu-Chen Hsu ,  Gregory Fredeman ,  Chorng-Lii Hwang ,  Toshiaki Kirihata ,  Dale E. Pontius

IPC分类号： G11C700

CPC分类号： G11C29/846 ,  G11C2207/104

摘要： A column redundancy system including a column redundancy apparatus for performing a redundancy swapping operation of column elements within the individual micro-cells. The column redundancy apparatus further includes a fuse information storage device, a first bank address decoding mechanism decodes a read bank address corresponding to a first micro-cell accessed for a read operation, and a second bank address decoding mechanism decodes a write bank address corresponding to a second micro-cell accessed for a write operation. If there is at least one defective column element contained within the first micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the first micro-cell. Likewise, if there is at least one defective column element contained within the second micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the second micro-cell.