公开(公告)号：US5483179A

公开(公告)日：1996-01-09

申请号：US230265

申请日：1994-04-20

申请人： Sang H. Dhong ,  Toshiaki Kirihata ,  Matthew R. Wordeman

发明人： Sang H. Dhong ,  Toshiaki Kirihata ,  Matthew R. Wordeman

IPC分类号： H03K17/687 ,  G05F3/24 ,  H03K19/0175 ,  H01L25/00

CPC分类号： G05F3/24

摘要： A device for controlling the voltage across an NMOS pull-up transistor including a source node which may be exposed to a variable voltage. The device further includes a gate node which may be exposed to a variable voltage. A control portion regulates the voltage applied to the gate node, wherein a differential in voltage between the source node and the gate node is limited to a desired level.

摘要翻译： 用于控制跨越NMOS上拉晶体管的电压的装置，其包括可能暴露于可变电压的源节点。 该器件还包括可以暴露于可变电压的栅极节点。 控制部分调节施加到栅极节点的电压，其中源节点和栅极节点之间的电压差被限制到期望的电平。

公开(公告)号：US5214603A

公开(公告)日：1993-05-25

申请号：US740758

申请日：1991-08-05

申请人： Sang H. Dhong ,  Wei Hwang ,  Lewis M. Terman ,  Matthew R. Wordeman

发明人： Sang H. Dhong ,  Wei Hwang ,  Lewis M. Terman ,  Matthew R. Wordeman

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10832

摘要： A folded bitline DRAM cell is described which includes a trench capacitor and a planar-configured access transistor. The access transistor is stacked over the capacitor and has a first terminal connected thereto. The access transistor includes a planar-oriented gate. A first wordline has a minor surface in contact with the gate and a major surface that is oriented orthogonally to the gate. An insulating pedestal is positioned adjacent the gate and a passing wordline is positioned on the pedestal, the passing wordline having a major surface parallel to the first wordline. In another embodiment, the folded bitline DRAM cell includes a vertically oriented access transistor having one terminal formed on the upper extent of a contact to the trench capacitor, to provide optimum electrical connection thereto.

公开(公告)号：US5336629A

公开(公告)日：1994-08-09

申请号：US975655

申请日：1992-11-13

申请人： Sang H. Dhong ,  Wei Hwang ,  Lewis M. Terman ,  Matthew R. Wordeman

发明人： Sang H. Dhong ,  Wei Hwang ,  Lewis M. Terman ,  Matthew R. Wordeman

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10832

摘要： A folded bitline DRAM cell is described which includes a trench capacitor and a planar-configured access transistor. The access transistor is stacked over the capacitor and has a first terminal connected thereto. The access transistor includes a planar-oriented gate. A first wordline has a minor surface in contact with the gate and a major surface that is oriented orthogonally to the gate. An insulating pedestal is positioned adjacent the gate and a passing wordline is positioned on the pedestal, the passing wordline having a major surface parallel to the first wordline. In another embodiment, the folded bitline DRAM cell includes a vertically oriented access transistor having one terminal formed on the upper extent of a contact to the trench capacitor, to provide optimum electrical connection thereto.

摘要翻译： 描述了折叠的位线DRAM单元，其包括沟槽电容器和平面配置的存取晶体管。 存取晶体管堆叠在电容器上，并具有与其连接的第一端子。 存取晶体管包括平面取向栅极。 第一字线具有与栅极接触的次表面和与栅极正交定向的主表面。 绝缘基座位于门附近，并且通过的字线位于基座上，通过的字线具有与第一字线平行的主表面。 在另一个实施例中，折叠的位线DRAM单元包括垂直定向的存取晶体管，其具有形成在与沟槽电容器的接触的上部范围上的一个端子，以提供与其的最佳电连接。

公开(公告)号：US5339274A

公开(公告)日：1994-08-16

申请号：US969644

申请日：1992-10-30

申请人： Sang H. Dhong ,  Toshiaki Kirihata ,  Hyun J. Shin ,  Toshio Sunaga ,  Yoichi Taira ,  Lewis M. Terman

发明人： Sang H. Dhong ,  Toshiaki Kirihata ,  Hyun J. Shin ,  Toshio Sunaga ,  Yoichi Taira ,  Lewis M. Terman

IPC分类号： G11C11/409 ,  G11C11/407 ,  G11C11/4094 ,  G11C7/00

CPC分类号： G11C11/4094

摘要： A sensing technique uses a variable precharge voltage sensing with a single bitline swing in a DRAM cell or array of DRAM cells so that the power dissipation is reduced. The bitline precharge voltage varies from one RAS cycle to the next RAS cycle depending upon the level of the data in the accessed cells. Such an arrangement eliminates the need for a reference voltage generator since the precharge voltage is not the same voltage for each RAS cycle.

摘要翻译： 感测技术在DRAM单元或DRAM单元阵列中使用单个位线摆动的可变预充电电压感测，从而降低功耗。 位线预充电电压根据所访问的单元中的数据的电平而从一个RAS周期到下一个RAS周期变化。 这种布置消除了对参考电压发生器的需要，因为对于每个RAS周期，预充电电压不是相同的电压。

公开(公告)号：US5541887A

公开(公告)日：1996-07-30

申请号：US375025

申请日：1995-01-19

申请人： Sang H. Dhong ,  Wei Hwang ,  Toshiaki Kirihata

发明人： Sang H. Dhong ,  Wei Hwang ,  Toshiaki Kirihata

IPC分类号： G11C8/16 ,  G11C29/50 ,  G11C7/00

CPC分类号： G11C29/50 ,  G11C8/16

摘要： Sequentially terminated write enable pulses applied to respective input ports of a multi-port memory cell is effective to establish a priority among those input ports and provide unconditionally unambiguous writing to a memory cell when write operations are concurrently attempted at two or more ports of that cell, as may be encountered during rigorous testing procedures. Memory structure, particularly that of the input port circuits, is simplified and operational speed is enhanced since signal propagation through a comparator or logic circuit is avoided. Time required for testing of large memory arrays is also significantly reduced.

摘要翻译： 施加到多端口存储器单元的相应输入端口的顺序终止写入使能脉冲对于在这些输入端口之间建立优先级是有效的，并且当在该单元的两个或更多个端口同时尝试写入操作时，向存储器单元提供无条件地明确的写入 ，如在严格的测试程序中可能遇到的。 存储器结构，特别是输入端口电路的存储器结构被简化，并且由于避免了通过比较器或逻辑电路的信号传播，因此提高了操作速度。 大型存储器阵列测试所需的时间也大大减少。

公开(公告)号：US5257232A

公开(公告)日：1993-10-26

申请号：US847769

申请日：1992-03-05

申请人： Sang H. Dhong ,  Koji Kitamura ,  Toshiaki Kirihata ,  Toshio Sunaga

发明人： Sang H. Dhong ,  Koji Kitamura ,  Toshiaki Kirihata ,  Toshio Sunaga

IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C11/407 ,  G11C11/4091 ,  G11C13/00

CPC分类号： G11C11/4091 ,  G11C7/065

摘要： A sensing circuit for dynamic random access memory is disclosed including a pair of bitlines precharged to a first voltage before sensing. A sense amplifier circuit is provided having one node thereof being connected to an external power supply via a switching means including pulsed sense clocks. Control means is provided and is connected to the switching means for controlling the switching means such that the voltage of the power supply is coupled to the node of the sense amplifier for activation for a predetermined period of time, thereby limiting the swing for the high-going bitline to a second voltage lower than said power supply voltage and higher than the first voltage. The reduced bit-line swings are achieved by means of the pulsed sense clocks and the pulse widths for sense clocks are determined by means of a reference bitlines connected to the control means.

公开(公告)号：US5635858A

公开(公告)日：1997-06-03

申请号：US476299

申请日：1995-06-07

申请人： Chin-An Chang ,  Sang H. Dhong

发明人： Chin-An Chang ,  Sang H. Dhong

IPC分类号： G06F7/50 ,  G06F7/505 ,  H03K19/21

CPC分类号： G06F7/5055

摘要： A zero-stopping incrementer operates on the recognition that half of all digital values that require incrementing will be even numbers; that is, the least significant bit (LSB) is a binary "0". Incrementing such a number merely requires changing the LSB from a binary "0" to a binary "1". For odd numbers (i.e., those where the LSB is a binary "1"), the zero-stopping incrementer searches for the first binary "0" beginning with the LSB. Once found, that binary "0" is changed to a binary "1" and all the binary "1s" preceding it are changed to binary "0s". No change is required to the higher order bits following the first binary "0". This operation is very fast, the worst case being the case when all the binary bits of the number to be incremented are "1s". Nevertheless, the process is significantly increased, especially for 64-bit numbers which are processed by modern superscalar microprocessors. As compared with conventional incrementers using an adder-like scheme, the zero-stopping incrementer is about three times faster with power consumption less than half of the conventional incrementers.

摘要翻译： 零停止增量器对识别需要递增的所有数字值的一半将为偶数的操作。 也就是说，最低有效位（LSB）是二进制“0”。 增加这样的数字只需要将LSB从二进制“0”改变为二进制“1”。 对于奇数（即，LSB是二进制“1”的那些），零停止增量器从LSB开始搜索第一个二进制“0”。 一旦找到，该二进制“0”被改变为二进制“1”，并且其前面的所有二进制“1”被改变为二进制“0”。 在第一个二进制“0”之后的高阶位不需要改变。 这个操作是非常快的，最坏的情况就是要增加数字的所有二进制位都是“1s”的情况。 然而，该过程显着增加，特别是对于由现代超标量微处理器处理的64位数字。 与使用加法器方案的常规增量器相比，零停止增量器的功耗大约是常规加法器的一半的功耗的三倍。

公开(公告)号：US5453953A

公开(公告)日：1995-09-26

申请号：US281236

申请日：1994-07-27

申请人： Sang H. Dhong ,  Hyun J. Shin ,  Wei Hwang

发明人： Sang H. Dhong ,  Hyun J. Shin ,  Wei Hwang

IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C8/08 ,  H01L21/822 ,  H01L27/04 ,  G05F3/24

CPC分类号： G11C8/08 ,  G11C5/147

摘要： A voltage regulator is provided for controlling an on-chip voltage generator which produces a boost voltage across a charge reservoir for supply to one input of a plurality of word line drivers in a memory array. The regulator is configured such that the charge reservoir voltage will track the power supply voltage and the difference between the power supply voltage and the charge reservoir voltage will be maintained substantially constant over a predefined power supply range. The voltage regulator includes a bandgap reference generator, a first differential circuit for producing a transition voltage from the reference voltage and the power supply voltage, a first transistor for comparing the power supply voltage with the boost voltage, a second transistor for comparing the transition voltage with the reference voltage and a latching comparator for equating the signal outputs from the first and second transistors so as to define a control signal for the on-chip voltage generator. Along with further specific details of the voltage regulator, a preferred bandgap reference generator is described.

摘要翻译： 提供电压调节器用于控制片上电压发生器，其在电荷储存器两端产生升压电压，以供给存储器阵列中的多个字线驱动器的一个输入端。 调节器被配置为使得电荷储存器电压将跟踪电源电压，并且电源电压和电荷储存器电压之间的差将在预定义的电源范围内保持基本上恒定。 电压调节器包括带隙参考发生器，用于从参考电压和电源电压产生转换电压的第一差分电路，用于将电源电压与升压电压进行比较的第一晶体管，用于将转换电压 与参考电压和锁存比较器，用于使来自第一和第二晶体管的信号输出相等，以便为片上电压发生器定义一个控制信号。 除了电压调节器的进一步具体细节之外，还描述了优选的带隙参考发生器。

公开(公告)号：US5331189A

公开(公告)日：1994-07-19

申请号：US901281

申请日：1992-06-19

申请人： Kevin K. Chan ,  Sang H. Dhong ,  Dieter P. E. Kern ,  Young H. Lee

发明人： Kevin K. Chan ,  Sang H. Dhong ,  Dieter P. E. Kern ,  Young H. Lee

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78

CPC分类号： H01L29/513 ,  H01L27/115 ,  H01L29/7883

摘要： A flash EEPROM is produced comprising multiple MOS cells. In each cell, programming and erasing are performed through tunneling from the write gate to the floating gate and by tunneling from the floating gate to the erase gate, respectively. The directional dielectric employed is a multilayered structured (MLS) oxide, where thin oxide and thin polycrystalline silicon form alternating layers. The layering is asymmetric: that is, either the uppermost or bottommost layer is thicker than the other layers. As a result of this structure, the oxide exhibits directionality, that is, the tunneling is easier in one direction than the reverse direction, and significantly enhances the tunneling phenomena (tunneling current can be observed at as low as 4.7 V). In addition, the MLS oxide can be fabricated having different dielectric constants. The directionality, coupled with the separate write and erase gates, gives the new flash EEPROM cell a number of advantages: it is low-voltage operable, it is highly resistant to disturbance and has an easily scalable structure (that is, it can be made to operate at any given voltage within a specified scale).

摘要翻译： 制造包括多个MOS单元的快闪EEPROM。 在每个单元中，通过从写入栅极到浮动栅极的隧穿以及分别从浮置栅极到擦除栅极的隧穿来执行编程和擦除。 所采用的定向电介质是多层结构（MLS）氧化物，其中薄的氧化物和薄的多晶硅形成交替层。 分层是不对称的，也就是说，最上层或最底层比其他层厚。 作为该结构的结果，氧化物具有方向性，即，在一个方向上的隧道比反向更容易，并且显着增强了隧道现象（隧道电流可以在低至4.7V）。 此外，可以制造具有不同介电常数的MLS氧化物。 方向性与单独的写入和擦除门相结合，为新的快闪EEPROM单元提供了许多优点：它是低电压可操作的，它具有高度的抗干扰性，并且具有易于扩展的结构（即可以制成 在指定电压范围内工作）。

公开(公告)号：US5300800A

公开(公告)日：1994-04-05

申请号：US966893

申请日：1992-10-26

申请人： Gary B. Bronner ,  Sang H. Dhong ,  Wei Hwang

发明人： Gary B. Bronner ,  Sang H. Dhong ,  Wei Hwang

IPC分类号： H01L21/76 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/68 ,  H01L29/78 ,  H01L29/92

CPC分类号： H01L27/10829

摘要： Disclosed is a Dynamic Random Access Memory (DRAM) cell which includes a storage capacitor disposed in a trench formed in a semiconductor substrate and an access transistor disposed in a well which is opposite in conductivity type to that of the substrate and a buried oxide collar which surrounds an upper portion of the trench.

摘要翻译： 公开了一种动态随机存取存储器（DRAM）单元，其包括设置在形成在半导体衬底中的沟槽中的存储电容器和设置在与衬底的导电类型相反的阱中的存取晶体管和埋入氧化物环， 围绕沟槽的上部。