公开(公告)号：US09054210B2

公开(公告)日：2015-06-09

申请号：US13479679

申请日：2012-05-24

申请人： Sang-Jine Park ,  Doo-Sung Yun ,  Bo-Un Yoon ,  Jeong-Nam Han ,  Kee-Sang Kwon ,  Won-Sang Choi

发明人： Sang-Jine Park ,  Doo-Sung Yun ,  Bo-Un Yoon ,  Jeong-Nam Han ,  Kee-Sang Kwon ,  Won-Sang Choi

IPC分类号： H01L21/20 ,  H01L21/36 ,  H01L21/8234 ,  H01L21/285 ,  H01L21/02 ,  H01L29/78 ,  H01L21/768 ,  H01L21/311

CPC分类号： H01L21/823425 ,  H01L21/02063 ,  H01L21/28518 ,  H01L21/31116 ,  H01L21/76814 ,  H01L21/76897 ,  H01L21/823475 ,  H01L29/78

摘要： A method of fabricating a semiconductor device, the method including forming on a substrate a transistor that includes a gate electrode and a source and drain region, forming an interlayer insulating film on the transistor, forming a contact hole in the interlayer insulating film to expose a top surface of the source and drain region, and a thin film is formed at an interface between the contact hole and the exposed top surface of the source and drain region. The method further including selectively removing at least a portion of the thin film by performing an etching process in a non-plasma atmosphere, forming an ohmic contact film on the source and drain region where at least a portion of the thin film was selectively removed, and forming a contact plug by filling the contact hole with a conductive material.

摘要翻译： 一种制造半导体器件的方法，所述方法包括在衬底上形成包括栅极和源极和漏极区的晶体管，在所述晶体管上形成层间绝缘膜，在所述层间绝缘膜中形成接触孔以暴露出 源极和漏极区域的顶表面，并且在接触孔和源极和漏极区域的暴露顶表面之间的界面处形成薄膜。 该方法还包括通过在非等离子体气氛中进行蚀刻工艺来选择性地去除薄膜的至少一部分，在选择性地去除薄膜的至少一部分的源区和漏区上形成欧姆接触膜， 以及通过用导电材料填充接触孔来形成接触塞。

公开(公告)号：US08673724B2

公开(公告)日：2014-03-18

申请号：US13561245

申请日：2012-07-30

申请人： Sang-Jine Park ,  Kee-Sang Kwon ,  Doo-Sung Yun ,  Bo-Un Yoon ,  Jeong-Nam Han

发明人： Sang-Jine Park ,  Kee-Sang Kwon ,  Doo-Sung Yun ,  Bo-Un Yoon ,  Jeong-Nam Han

IPC分类号： H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/76224 ,  H01L29/0657 ,  H01L29/78 ,  H01L29/7848

摘要： Provided are methods of fabricating a semiconductor device that include providing a substrate that includes a first region having a gate pattern and a second region having a first trench and an insulating layer that fills the first trench. A portion of a sidewall of the first trench is exposed by etching part of the insulating layer and a first spacer is formed on a sidewall of the gate pattern. A second spacer is formed on the exposed sidewall of the first trench, wherein the first spacer and the second spacer are formed simultaneously.

摘要翻译： 提供制造半导体器件的方法，其包括提供包括具有栅极图案的第一区域和具有填充第一沟槽的第一沟槽和绝缘层的第二区域的衬底。 通过蚀刻绝缘层的一部分露出第一沟槽的侧壁的一部分，并且在栅极图案的侧壁上形成第一间隔物。 第二间隔件形成在第一沟槽的暴露的侧壁上，其中第一间隔件和第二间隔件同时形成。

公开(公告)号：US20130115759A1

公开(公告)日：2013-05-09

申请号：US13561245

申请日：2012-07-30

申请人： Sang-Jine Park ,  Kee-Sang Kwon ,  Doo-Sung Yun ,  Bo-Un Yoon ,  Jeong-Nam Han

发明人： Sang-Jine Park ,  Kee-Sang Kwon ,  Doo-Sung Yun ,  Bo-Un Yoon ,  Jeong-Nam Han

IPC分类号： H01L21/20

CPC分类号： H01L29/66636 ,  H01L21/76224 ,  H01L29/0657 ,  H01L29/78 ,  H01L29/7848

摘要： Provided are methods of fabricating a semiconductor device that include providing a substrate that includes a first region having a gate pattern and a second region having a first trench and an insulating layer that fills the first trench. A portion of a sidewall of the first trench is exposed by etching part of the insulating layer and a first spacer is formed on a sidewall of the gate pattern. A second spacer is formed on the exposed sidewall of the first trench, wherein the first spacer and the second spacer are formed simultaneously.

摘要翻译： 提供制造半导体器件的方法，其包括提供包括具有栅极图案的第一区域和具有填充第一沟槽的第一沟槽和绝缘层的第二区域的衬底。 通过蚀刻绝缘层的一部分露出第一沟槽的侧壁的一部分，并且在栅极图案的侧壁上形成第一间隔物。 第二间隔件形成在第一沟槽的暴露的侧壁上，其中第一间隔件和第二间隔件同时形成。

公开(公告)号：US08709942B2

公开(公告)日：2014-04-29

申请号：US13488478

申请日：2012-06-05

申请人： Sang-Jine Park ,  Kee-Sang Kwon ,  Doo-Sung Yun ,  Bo-Un Yoon ,  Il-Young Yoon ,  Jeong-Nam Han

发明人： Sang-Jine Park ,  Kee-Sang Kwon ,  Doo-Sung Yun ,  Bo-Un Yoon ,  Il-Young Yoon ,  Jeong-Nam Han

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816

摘要： In a method for fabricating a semiconductor device, a substrate is provided including an interlayer dielectric layer and first and second hard mask patterns sequentially stacked thereon. A first trench is provided in the interlayer dielectric layer through the second hard mask pattern and the first hard mask pattern. A filler material is provided on the interlayer dielectric layer and the second hard mask pattern to fill the first trench. An upper portion of the second hard mask pattern is exposed by partially removing the filler material. The second hard mask pattern is removed, and remaining filler material is removed from the first trench. A wiring is formed by filling the first trench with a conductive material.

摘要翻译： 在制造半导体器件的方法中，提供了包括层间介电层和顺序堆叠在其上的第一和第二硬掩模图案的衬底。 第一沟槽通过第二硬掩模图案和第一硬掩模图案设置在层间介质层中。 在层间介电层和第二硬掩模图案上设置填充材料以填充第一沟槽。 通过部分去除填充材料来暴露第二硬掩模图案的上部。 去除第二硬掩模图案，并且从第一沟槽去除剩余的填充材料。 通过用导电材料填充第一沟槽来形成布线。

公开(公告)号：US20130023119A1

公开(公告)日：2013-01-24

申请号：US13488478

申请日：2012-06-05

申请人： Sang-Jine Park ,  Kee-Sang Kwon ,  Doo-Sung Yun ,  Bo-Un Yoon ,  Il- Young Yoon ,  Jeong-Nam Han

发明人： Sang-Jine Park ,  Kee-Sang Kwon ,  Doo-Sung Yun ,  Bo-Un Yoon ,  Il- Young Yoon ,  Jeong-Nam Han

IPC分类号： H01L21/768

CPC分类号： H01L21/76808 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816

摘要： In a method for fabricating a semiconductor device, a substrate is provided including an interlayer dielectric layer and first and second hard mask patterns sequentially stacked thereon. A first trench is provided in the interlayer dielectric layer through the second hard mask pattern and the first hard mask pattern. A filler material is provided on the interlayer dielectric layer and the second hard mask pattern to fill the first trench. An upper portion of the second hard mask pattern is exposed by partially removing the filler material. The second hard mask pattern is removed, and remaining filler material is removed from the first trench. A wiring is formed by filling the first trench with a conductive material.

摘要翻译： 在制造半导体器件的方法中，提供了包括层间介电层和顺序堆叠在其上的第一和第二硬掩模图案的衬底。 第一沟槽通过第二硬掩模图案和第一硬掩模图案设置在层间介质层中。 在层间介电层和第二硬掩模图案上设置填充材料以填充第一沟槽。 通过部分去除填充材料来暴露第二硬掩模图案的上部。 去除第二硬掩模图案，并且从第一沟槽去除剩余的填充材料。 通过用导电材料填充第一沟槽来形成布线。

公开(公告)号：US08404580B2

公开(公告)日：2013-03-26

申请号：US13444175

申请日：2012-04-11

申请人： Sang-Jine Park ,  Bo-Un Yoon ,  Jeong-Nam Han ,  Yoon-Hae Kim ,  Doo-Sung Yun

发明人： Sang-Jine Park ,  Bo-Un Yoon ,  Jeong-Nam Han ,  Yoon-Hae Kim ,  Doo-Sung Yun

IPC分类号： H01L21/4763

CPC分类号： H01L21/31144 ,  H01L21/76804 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76877

摘要： In a method for fabricating a semiconductor device, a semiconductor device is provided including an interlayer dielectric film and first and second hard mask patterns sequentially stacked thereon. A first trench is provided in the interlayer dielectric film through the second hard mask pattern and the first hard mask pattern. A filler material is provided on the interlayer dielectric film and the first and second hard mask patterns to fill the first trench. First and second hard mask trimming patterns are formed by trimming sidewalls of the first and second hard mask patterns and removing the filler material to expose the first trench. A damascene wire is formed by filling the first trench with a conductive material.

摘要翻译： 在制造半导体器件的方法中，提供了半导体器件，其包括层间绝缘膜和顺序堆叠在其上的第一和第二硬掩模图案。 第一沟槽通过第二硬掩模图案和第一硬掩模图案设置在层间电介质膜中。 在层间电介质膜和第一和第二硬掩模图案上设置填充材料以填充第一沟槽。 通过修剪第一和第二硬掩模图案的侧壁并去除填充材料以暴露第一沟槽而形成第一和第二硬掩模修剪图案。 通过用导电材料填充第一沟槽来形成镶嵌线。

公开(公告)号：US20120309189A1

公开(公告)日：2012-12-06

申请号：US13444175

申请日：2012-04-11

申请人： Sang-Jine Park ,  Bo-Un Yoon ,  Jeong-Nam Han ,  Yoon-Hae Kim ,  Doo-Sung Yun

发明人： Sang-Jine Park ,  Bo-Un Yoon ,  Jeong-Nam Han ,  Yoon-Hae Kim ,  Doo-Sung Yun

IPC分类号： H01L21/768

CPC分类号： H01L21/31144 ,  H01L21/76804 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76877

摘要： In a method for fabricating a semiconductor device, a semiconductor device is provided including an interlayer dielectric film and first and second hard mask patterns sequentially stacked thereon. A first trench is provided in the interlayer dielectric film through the second hard mask pattern and the first hard mask pattern. A filler material is provided on the interlayer dielectric film and the first and second hard mask patterns to fill the first trench. First and second hard mask trimming patterns are formed by trimming sidewalls of the first and second hard mask patterns and removing the filler material to expose the first trench. A damascene wire is formed by filling the first trench with a conductive material.

摘要翻译： 在制造半导体器件的方法中，提供了半导体器件，其包括层间绝缘膜和顺序堆叠在其上的第一和第二硬掩模图案。 第一沟槽通过第二硬掩模图案和第一硬掩模图案设置在层间电介质膜中。 在层间电介质膜和第一和第二硬掩模图案上设置填充材料以填充第一沟槽。 通过修剪第一和第二硬掩模图案的侧壁并去除填充材料以暴露第一沟槽而形成第一和第二硬掩模修剪图案。 通过用导电材料填充第一沟槽来形成镶嵌线。

公开(公告)号：US10192782B2

公开(公告)日：2019-01-29

申请号：US14747316

申请日：2015-06-23

申请人： Woojin Lee ,  VietHa Nguyen ,  Wookyung You ,  Doo-Sung Yun ,  Hyunbae Lee ,  Byunghee Kim ,  Sang Hoon Ahn ,  Seungyong Yoo ,  Naein Lee ,  Hoyun Jeon

发明人： Woojin Lee ,  VietHa Nguyen ,  Wookyung You ,  Doo-Sung Yun ,  Hyunbae Lee ,  Byunghee Kim ,  Sang Hoon Ahn ,  Seungyong Yoo ,  Naein Lee ,  Hoyun Jeon

IPC分类号： H01L21/768 ,  H01L21/31 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213

摘要： A method of manufacturing the semiconductor device includes providing a first interlayer dielectric layer having a conductive pattern, sequentially forming a first etch stop layer, a second etch stop layer, a second interlayer dielectric layer and a mask pattern on the first interlayer dielectric layer, forming an opening in the second interlayer dielectric layer using the mask pattern as a mask, the opening exposing the second etch stop layer, and performing an etching process including simultaneously removing the mask pattern and the second etch stop layer exposed by the opening to expose the first etch stop layer.

公开(公告)号：US20120091422A1

公开(公告)日：2012-04-19

申请号：US13221242

申请日：2011-08-30

申请人： Sukhun Choi ,  Boun Yoon ,  Kevin Ahn ,  Doo-Sung Yun

发明人： Sukhun Choi ,  Boun Yoon ,  Kevin Ahn ,  Doo-Sung Yun

IPC分类号： H01L45/00

CPC分类号： H01L27/2409 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06

摘要： According to a method of fabricating the semiconductor memory device, a contact plug can be protected while mold openings are formed. A semiconductor memory device may include a mold dielectric layer on an entire surface of a substrate, the substrate including a first region and a second region. A contact plug may be provided in a contact hole formed through the mold dielectric layer in the first region. A variable resistor may be provided in a mold opening foamed through the mold dielectric layer in the second region. An upper surface of the contact plug may be at a level equal to or lower than an upper surface of the mold dielectric layer.

摘要翻译： 根据制造半导体存储器件的方法，可以在形成开口的同时保护接触塞。 半导体存储器件可以在衬底的整个表面上包括模具电介质层，该衬底包括第一区域和第二区域。 接触插塞可以设置在通过第一区域中的模具电介质层形成的接触孔中。 可变电阻器可以设置在通过第二区域中的模具电介质层发泡的模制开口中。 接触插塞的上表面可以处于等于或低于模具电介质层的上表面的水平。

公开(公告)号：US08766232B2

公开(公告)日：2014-07-01

申请号：US13221242

申请日：2011-08-30

申请人： Sukhun Choi ,  Boun Yoon ,  Kevin Ahn ,  Doo-Sung Yun

发明人： Sukhun Choi ,  Boun Yoon ,  Kevin Ahn ,  Doo-Sung Yun

IPC分类号： H01L47/00 ,  H01L27/24 ,  H01L45/00

CPC分类号： H01L27/2409 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06

摘要： According to a method of fabricating the semiconductor memory device, a contact plug can be protected while mold openings are formed. A semiconductor memory device may include a mold dielectric layer on an entire surface of a substrate, the substrate including a first region and a second region. A contact plug may be provided in a contact hole formed through the mold dielectric layer in the first region. A variable resistor may be provided in a mold opening formed through the mold dielectric layer in the second region. An upper surface of the contact plug may be at a level equal to or lower than an upper surface of the mold dielectric layer.

摘要翻译： 根据制造半导体存储器件的方法，可以在形成开口的同时保护接触塞。 半导体存储器件可以在衬底的整个表面上包括模具电介质层，该衬底包括第一区域和第二区域。 接触插塞可以设置在通过第一区域中的模具电介质层形成的接触孔中。 可变电阻器可以设置在通过第二区域中的模具电介质层形成的模具开口中。 接触插塞的上表面可以处于等于或低于模具电介质层的上表面的水平。