公开(公告)号：US08953376B2

公开(公告)日：2015-02-10

申请号：US13401151

申请日：2012-02-21

申请人： Sang-Wan Nam ,  Chiweon Yoon ,  Jung-Soo Kim

发明人： Sang-Wan Nam ,  Chiweon Yoon ,  Jung-Soo Kim

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C16/26 ,  H01L27/115

CPC分类号： G11C16/26 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

摘要： According to example embodiments, a read method of a nonvolatile memory device includes Disclosed is a read method of a nonvolatile memory device which includes selecting one of a plurality of vertical strings in a nonvolatile memory device, judging a channel length between a common source line and a selected one of the plurality of vertical strings, selecting a sensing manner corresponding to the judged channel length, and performing a sensing operation according to the selected sensing manner. The plurality of vertical strings may extend in a direction perpendicular to a substrate of the nonvolatile memory device.

摘要翻译： 根据示例实施例，非易失性存储器件的读取方法包括：非易失性存储器件的读取方法，其包括选择非易失性存储器件中的多个垂直条之一，判断公共源极线和 选择多个垂直串中的一个，选择与所判断的信道长度相对应的感测方式，以及根据所选择的感测方式执行感测操作。 多个垂直线可以在垂直于非易失性存储器件的衬底的方向上延伸。

公开(公告)号：US10056148B2

公开(公告)日：2018-08-21

申请号：US15342027

申请日：2016-11-02

申请人： Donghun Kwak ,  Daeseok Byeon ,  Chiweon Yoon

发明人： Donghun Kwak ,  Daeseok Byeon ,  Chiweon Yoon

IPC分类号： G11C11/00 ,  G11C16/08 ,  G11C16/04

CPC分类号： G11C16/08 ,  G11C16/0483

摘要： A nonvolatile memory device includes a memory cell array having a first plane and a second plane and an address decoder connected to the first plane through first string select lines and connected to the second plane through second string select line. The address decoder provides a string select signal and a string unselect signal to the first and second string select lines. The address decoder independently provides the string select signal and the string unselect signal to the first and second string select lines in each plane based on different string select line addresses corresponding to the first and second planes.

公开(公告)号：US08743617B2

公开(公告)日：2014-06-03

申请号：US13429899

申请日：2012-03-26

申请人： Sang-Won Shim ,  Dong-Hun Kwak ,  Doosub Lee ,  Chiweon Yoon

发明人： Sang-Won Shim ,  Dong-Hun Kwak ,  Doosub Lee ,  Chiweon Yoon

IPC分类号： G11C11/34

CPC分类号： G11C5/147 ,  G11C16/10 ,  G11C16/30 ,  G11C16/3418 ,  H01L27/11582

摘要： According to example embodiments, a nonvolatile memory device includes a memory cell array including a plurality of memory cells stacked on a substrate, a plurality of word lines connected with the memory cell array, a plurality of pass voltage generators, and a voltage control circuit. The pass voltage generators each include a plurality of current paths and are configured to generate pass driving signals applied to unselected word lines of the plurality of word lines. The voltage control circuit is configured to control rising slopes of the pass driving signals generated from the plurality of pass voltage generators, based on adjusting the number of current paths in each pass voltage generator used to generate each driving signal.

摘要翻译： 根据示例性实施例，非易失性存储器件包括存储单元阵列，其包括堆叠在衬底上的多个存储单元，与存储单元阵列连接的多个字线，多个通过电压发生器和电压控制电路。 通过电压发生器各自包括多个电流路径，并且被配置为产生施加到多个字线的未选字线的通过驱动信号。 电压控制电路被配置为基于调整用于产生每个驱动信号的每个通过电压发生器中的电流路径的数量来控制从多个通过电压发生器产生的通过驱动信号的上升沿。

公开(公告)号：US09842654B2

公开(公告)日：2017-12-12

申请号：US14996249

申请日：2016-01-15

申请人： Ji-Sang Lee ,  Donghun Kwak ,  Daeseok Byeon ,  Chiweon Yoon

发明人： Ji-Sang Lee ,  Donghun Kwak ,  Daeseok Byeon ,  Chiweon Yoon

IPC分类号： G11C11/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/04 ,  G11C16/24 ,  G11C11/56

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26

摘要： A nonvolatile memory includes a memory cell array, a row decoder circuit, and a page buffer circuit. The row decoder circuit applies a turn-on voltage to string selection lines, which are connected to string selection transistors of a selected memory block, at a first precharge operation in response to a write command received from an external device. The page buffer circuit applies, in response to the write command, a first voltage to bit lines, which are connected to the string selection transistors, through a first precharge circuit at the first precharge operation regardless of loaded data and applies the first voltage and a second voltage to the bit lines through a second precharge circuit at a second precharge operation based on the loaded data. During the first precharge operation, write data is loaded onto the page buffer circuit.