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    Charge trap memory device
    1.
    发明申请
    Charge trap memory device 审中-公开
    电荷陷阱记忆装置

    公开(公告)号：US20080087944A1

    公开(公告)日：2008-04-17

    申请号：US11905769

    申请日：2007-10-04

    申请人： Sang-min Shin ,  Kwang-soo Seol ,  Sang-Jin Park ,  Jung-hun Sung ,  Sang-moo Choi

    发明人： Sang-min Shin ,  Kwang-soo Seol ,  Sang-Jin Park ,  Jung-hun Sung ,  Sang-moo Choi

    IPC分类号： H01L29/792

    CPC分类号： H01L29/42332 ,  H01L29/40114

    摘要： A charge trap memory device may include a tunnel insulating layer formed on a substrate. A charge trap layer may be formed on the tunnel insulating layer, wherein the charge trap layer is a higher-k dielectric insulating layer doped with one or more transition metals. The tunneling insulating layer may be relatively non-reactive with respect to metals in the charge trap layer. The tunneling insulating layer may also reduce or prevent metals in the charge trap layer from diffusing into the substrate.

    摘要翻译： 电荷陷阱存储器件可以包括形成在衬底上的隧道绝缘层。 电荷陷阱层可以形成在隧道绝缘层上，其中电荷陷阱层是掺杂有一种或多种过渡金属的较高k介电绝缘层。 隧穿绝缘层相对于电荷陷阱层中的金属可能是相对不反应的。 隧道绝缘层还可以减少或防止电荷陷阱层中的金属扩散到衬底中。

    Semiconductor memory device including recessed control gate electrode
    2.
    发明授权
    Semiconductor memory device including recessed control gate electrode 失效
    半导体存储器件包括凹入控制栅电极

    公开(公告)号：US07732855B2

    公开(公告)日：2010-06-08

    申请号：US11808982

    申请日：2007-06-14

    申请人： Sang-jin Park ,  Kwang-soo Seol ,  Yoon-dong Park ,  Sang-min Shin ,  In-jun Hwang ,  Sang-moo Choi ,  Ju-hee Park

    发明人： Sang-jin Park ,  Kwang-soo Seol ,  Yoon-dong Park ,  Sang-min Shin ,  In-jun Hwang ,  Sang-moo Choi ,  Ju-hee Park

    IPC分类号： H01L21/28

    CPC分类号： H01L29/42324 ,  G11C16/0408 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42336 ,  H01L29/4234 ,  H01L29/42352 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

    摘要： A semiconductor memory device may include a semiconductor substrate, at least one control gate electrode, at least one storage node layer, at least one tunneling insulating layer, at least one blocking insulating layer, and/or first and second channel regions. The at least one control gate electrode may be recessed into the semiconductor substrate. The at least one storage node layer may be between a sidewall of the at least one control gate electrode and the semiconductor substrate. The at least one tunneling insulating layer may be between the at least one storage node layer and the at least one control gate electrode. The at least one blocking insulating layer may be between the storage node layer and the control gate electrode. The first and second channel regions may be between the at least one tunneling insulating layer and the semiconductor substrate to surround at least a portion of the sidewall of the control gate electrode and/or may be separated from each other.

    摘要翻译： 半导体存储器件可以包括半导体衬底，至少一个控制栅电极，至少一个存储节点层，至少一个隧道绝缘层，至少一个阻挡绝缘层和/或第一和第二沟道区。 至少一个控制栅电极可以凹进到半导体衬底中。 所述至少一个存储节点层可以在所述至少一个控制栅电极的侧壁和所述半导体衬底之间。 所述至少一个隧道绝缘层可以在所述至少一个存储节点层和所述至少一个控制栅电极之间。 所述至少一个阻挡绝缘层可以在所述存储节点层和所述控制栅电极之间。 第一和第二沟道区可以在至少一个隧道绝缘层和半导体衬底之间，以围绕控制栅电极的侧壁的至少一部分和/或可以彼此分离。

    Semiconductor memory device including recessed control gate electrode
    4.
    发明申请
    Semiconductor memory device including recessed control gate electrode 失效
    半导体存储器件包括凹入控制栅电极

    公开(公告)号：US20080093662A1

    公开(公告)日：2008-04-24

    申请号：US11808982

    申请日：2007-06-14

    申请人： Sang-jin Park ,  Kwang-soo Seol ,  Yoon-dong Park ,  Sang-min Shin ,  In-jun Hwang ,  Sang-moo Choi ,  Ju-hee Park

    发明人： Sang-jin Park ,  Kwang-soo Seol ,  Yoon-dong Park ,  Sang-min Shin ,  In-jun Hwang ,  Sang-moo Choi ,  Ju-hee Park

    IPC分类号： H01L29/792

    CPC分类号： H01L29/42324 ,  G11C16/0408 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42336 ,  H01L29/4234 ,  H01L29/42352 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

    摘要： A semiconductor memory device may include a semiconductor substrate, at least one control gate electrode, at least one storage node layer, at least one tunneling insulating layer, at least one blocking insulating layer, and/or first and second channel regions. The at least one control gate electrode may be recessed into the semiconductor substrate. The at least one storage node layer may be between a sidewall of the at least one control gate electrode and the semiconductor substrate. The at least one tunneling insulating layer may be between the at least one storage node layer and the at least one control gate electrode. The at least one blocking insulating layer may be between the storage node layer and the control gate electrode. The first and second channel regions may be between the at least one tunneling insulating layer and the semiconductor substrate to surround at least a portion of the sidewall of the control gate electrode and/or may be separated from each other.

    摘要翻译： 半导体存储器件可以包括半导体衬底，至少一个控制栅电极，至少一个存储节点层，至少一个隧道绝缘层，至少一个阻挡绝缘层和/或第一和第二沟道区。 至少一个控制栅电极可以凹进到半导体衬底中。 所述至少一个存储节点层可以在所述至少一个控制栅电极的侧壁和所述半导体衬底之间。 所述至少一个隧道绝缘层可以在所述至少一个存储节点层和所述至少一个控制栅电极之间。 所述至少一个阻挡绝缘层可以在所述存储节点层和所述控制栅电极之间。 第一和第二沟道区可以在至少一个隧道绝缘层和半导体衬底之间，以围绕控制栅电极的侧壁的至少一部分和/或可以彼此分离。

    Semiconductor memory device having an alloy metal gate electrode and method of manufacturing the same
    7.
    发明申请
    Semiconductor memory device having an alloy metal gate electrode and method of manufacturing the same 审中-公开
    具有合金金属栅电极的半导体存储器件及其制造方法

    公开(公告)号：US20070190721A1

    公开(公告)日：2007-08-16

    申请号：US11655180

    申请日：2007-01-19

    申请人： Young-kwan Cha ,  Young-soo Park ,  Kwang-soo Seol ,  Sang-jin Park ,  Sang-min Shin

    发明人： Young-kwan Cha ,  Young-soo Park ,  Kwang-soo Seol ,  Sang-jin Park ,  Sang-min Shin

    IPC分类号： H01L21/336

    CPC分类号： H01L29/513 ,  H01L21/28088 ,  H01L29/40117 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/792

    摘要： A semiconductor memory device having an alloy gate electrode layer and method of manufacturing the same are provided. The semiconductor memory device may include a semiconductor substrate having a first impurity region and a second impurity region. The semiconductor memory device may include a gate structure formed on the semiconductor substrate and contacting the first and second impurity regions. The gate structure may include an alloy gate electrode layer formed of a first metal and a second metal. The first metal may be a noble metal. The second metal may include at least one of aluminum (Al) and titanium (Ti), gallium (Ga), indium (In), tin (Sb), thallium (Tl), bismuth (Bi) and lead (Pb).

    摘要翻译： 提供了具有合金栅电极层的半导体存储器件及其制造方法。 半导体存储器件可以包括具有第一杂质区和第二杂质区的半导体衬底。 半导体存储器件可以包括形成在半导体衬底上并与第一和第二杂质区接触的栅极结构。 栅极结构可以包括由第一金属和第二金属形成的合金栅极电极层。 第一种金属可能是贵金属。 第二金属可以包括铝（Al）和钛（Ti），镓（Ga），铟（In），锡（Sb），铊（Tl），铋（Bi）和铅（Pb）中的至少一种。

    Charge trap layer for a charge trap semiconductor memory device and method of manufacturing the same
    8.
    发明授权
    Charge trap layer for a charge trap semiconductor memory device and method of manufacturing the same 有权
    用于电荷陷阱半导体存储器件的电荷陷阱层及其制造方法

    公开(公告)号：US07795159B2

    公开(公告)日：2010-09-14

    申请号：US11987425

    申请日：2007-11-30

    申请人： Kwang-soo Seol ,  Yo-sep Min ,  Sang-min Shin

    发明人： Kwang-soo Seol ,  Yo-sep Min ,  Sang-min Shin

    IPC分类号： H01L21/31

    CPC分类号： H01L29/792 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/7883 ,  Y10T428/31678

    摘要： Provided are a charge trap semiconductor memory device including a charge trap layer on a semiconductor substrate, and a method of manufacturing the charge trap semiconductor memory device. The method includes: (a) coating a first precursor material on a surface of a semiconductor substrate to be deposited and oxidizing the first precursor material to form a first layer formed of an insulating material; (b) coating a second precursor material formed of metallicity on the first layer; (c) supplying the first precursor material on the surface coated with the second precursor material to substitute the second precursor material with the first precursor material; and (d) oxidizing the first and second precursor materials obtained in (c) to form a second layer formed of an insulating material and a metal impurity, and (a) through (d) are performed at least one time to form a charge trap layer having a structure in which the metal impurity is isolated in the insulating material.

    摘要翻译： 提供了一种在半导体衬底上包括电荷陷阱层的电荷陷阱半导体存储器件，以及制造电荷阱半导体存储器件的方法。 该方法包括：（a）在待沉积的半导体衬底的表面上涂覆第一前体材料并氧化第一前体材料以形成由绝缘材料形成的第一层; （b）在第一层上涂覆由金属性形成的第二前体材料; （c）在涂覆有第二前体材料的表面上提供第一前体材料以用第一前体材料代替第二前体材料; 和（d）氧化由（c）中得到的第一和第二前体材料以形成由绝缘材料和金属杂质形成的第二层，并且（a）至（d）至少进行一次以形成电荷阱 具有金属杂质在绝缘材料中隔离的结构的层。

    Nonvolatile semiconductor memory device and method of manufacturing the same
    9.
    发明申请
    Nonvolatile semiconductor memory device and method of manufacturing the same 审中-公开
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US20100323509A1

    公开(公告)日：2010-12-23

    申请号：US12805823

    申请日：2010-08-20

    申请人： Sang-min Shin ,  Kwang-soo Seol ,  Young-gu Jin

    发明人： Sang-min Shin ,  Kwang-soo Seol ,  Young-gu Jin

    IPC分类号： H01L21/283

    CPC分类号： H01L29/792 ,  H01L29/40117 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/513 ,  H01L29/7881

    摘要： Provided is a nonvolatile semiconductor memory device and a method of manufacturing the same. The nonvolatile semiconductor memory device may include a tunnel insulating layer formed on a semiconductor substrate, a charge trap layer including a dielectric layer doped with a transition metal formed on the tunnel insulating layer, a blocking insulating layer formed on the charge trap layer, and a gate electrode formed on the blocking insulating layer. The dielectric layer may be a high-k dielectric layer, for example, a HfO2 layer. Thus, the data retention characteristics of the nonvolatile semiconductor memory device may be improved because a deeper charge trap may be formed by doping the high-k dielectric layer with a transition metal.

    摘要翻译： 提供一种非易失性半导体存储器件及其制造方法。 非易失性半导体存储器件可以包括形成在半导体衬底上的隧道绝缘层，包含掺杂在隧道绝缘层上形成的过渡金属的电介质层的电荷陷阱层，形成在电荷陷阱层上的阻挡绝缘层，以及 栅电极形成在阻挡绝缘层上。 电介质层可以是高k电介质层，例如HfO 2层。 因此，可以通过用过渡金属掺杂高k电介质层来形成更深的电荷陷阱来提高非易失性半导体存储器件的数据保持特性。

    Charge trap layer for a charge trap semiconductor memory device and method of manufacturing the same
    10.
    发明申请
    Charge trap layer for a charge trap semiconductor memory device and method of manufacturing the same 有权
    用于电荷陷阱半导体存储器件的电荷陷阱层及其制造方法

    公开(公告)号：US20080131710A1

    公开(公告)日：2008-06-05

    申请号：US11987425

    申请日：2007-11-30

    申请人： Kwang-soo Seol ,  Yo-sep Min ,  Sang-min Shin

    发明人： Kwang-soo Seol ,  Yo-sep Min ,  Sang-min Shin

    IPC分类号： B32B15/04 ,  H01L21/31 ,  H01L29/792

    CPC分类号： H01L29/792 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/7883 ,  Y10T428/31678

    摘要： Provided are a charge trap semiconductor memory device including a charge trap layer on a semiconductor substrate, and a method of manufacturing the charge trap semiconductor memory device. The method includes: (a) coating a first precursor material on a surface of a semiconductor substrate to be deposited and oxidizing the first precursor material to form a first layer formed of an insulating material; (b) coating a second precursor material formed of metallicity on the first layer; (c) supplying the first precursor material on the surface coated with the second precursor material to substitute the second precursor material with the first precursor material; and (d) oxidizing the first and second precursor materials obtained in (c) to form a second layer formed of an insulating material and a metal impurity, and (a) through (d) are performed at least one time to form a charge trap layer having a structure in which the metal impurity is isolated in the insulating material.

    摘要翻译： 提供了一种在半导体衬底上包括电荷陷阱层的电荷陷阱半导体存储器件，以及制造电荷阱半导体存储器件的方法。 该方法包括：（a）在要沉积的半导体衬底的表面上涂覆第一前体材料并氧化第一前体材料以形成由绝缘材料形成的第一层; （b）在第一层上涂覆由金属性形成的第二前体材料; （c）在涂覆有第二前体材料的表面上提供第一前体材料以用第一前体材料代替第二前体材料; 和（d）氧化由（c）中得到的第一和第二前体材料以形成由绝缘材料和金属杂质形成的第二层，并且（a）至（d）至少进行一次以形成电荷阱 具有金属杂质在绝缘材料中隔离的结构的层。