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    Bottom gate thin film transistor and method of manufacturing the same
    1.
    发明授权
    Bottom gate thin film transistor and method of manufacturing the same 失效
    底栅薄膜晶体管及其制造方法

    公开(公告)号：US07629207B2

    公开(公告)日：2009-12-08

    申请号：US11692716

    申请日：2007-03-28

    申请人： Hyuck Lim ,  Young-soo Park ,  Wenxu Xianyu ,  Young-kwan Cha

    发明人： Hyuck Lim ,  Young-soo Park ,  Wenxu Xianyu ,  Young-kwan Cha

    IPC分类号： H01L21/00 ,  H01L21/84

    CPC分类号： H01L29/78678 ,  H01L21/268 ,  H01L27/1285 ,  H01L29/66765 ,  H01L29/78609 ,  H01L29/78684 ,  H01L29/78696

    摘要： A method of manufacturing a bottom gate thin film transistor (“TFT”) in which a polycrystalline channel region having a large grain size is formed relatively simply and easily. The method of manufacturing a bottom gate thin film transistor includes forming a bottom gate electrode on a substrate, forming a gate insulating layer on the substrate to cover the bottom gate electrode, forming an amorphous semiconductor layer, an N-type semiconductor layer and an electrode layer on the gate insulating layer sequentially, etching an electrode region and an N-type semiconductor layer region formed on the bottom gate electrode sequentially to expose an amorphous semiconductor layer region, melting the amorphous semiconductor layer region using a laser annealing method, and crystallizing the melted amorphous semiconductor layer region to form a laterally grown polycrystalline channel region.

    摘要翻译： 相对简单且容易地形成具有大晶粒尺寸的多晶沟道区的底栅薄膜晶体管（“TFT”）的制造方法。 制造底栅极薄膜晶体管的方法包括在衬底上形成底栅电极，在衬底上形成栅极绝缘层以覆盖底栅电极，形成非晶半导体层，N型半导体层和电极 依次在栅极绝缘层上蚀刻形成在底栅电极上的电极区域和N型半导体层区域，以暴露非晶半导体层区域，使用激光退火法熔化非晶半导体层区域，并使 熔融的非晶半导体层区域以形成横向生长的多晶沟道区域。

    Nonvolatile memory devices including floating gates formed of silicon nano-crystals and methods of manufacturing the same
    2.
    发明申请
    Nonvolatile memory devices including floating gates formed of silicon nano-crystals and methods of manufacturing the same 审中-公开
    包括由硅纳米晶体形成的浮动栅极的非易失性存储器件及其制造方法

    公开(公告)号：US20070267679A1

    公开(公告)日：2007-11-22

    申请号：US11723020

    申请日：2007-03-15

    申请人： Young-kwan Cha ,  Suk-ho Choi ,  Kyu-il Han ,  Young-soo Park ,  Sang-jin Park ,  Yong-min Park

    发明人： Young-kwan Cha ,  Suk-ho Choi ,  Kyu-il Han ,  Young-soo Park ,  Sang-jin Park ,  Yong-min Park

    IPC分类号： H01L29/788 ,  H01L21/336

    CPC分类号： H01L29/42332 ,  B82Y10/00 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/7881

    摘要： A memory device includes a gate stack on a substrate. The gate stack is disposed between a source and a drain. The gate stack includes a tunneling film, storage node, and control oxide film. A thickness of the control oxide film is greater than or equal to about 5 nm and less than or equal to about 30 nm. A method of manufacturing a memory device, including a gate stack on a substrate, wherein the gate stack is disposed between a source and a drain, includes: sequentially forming a tunneling film, a first silicon-rich oxide film, and a control oxide film on the substrate, wherein the first silicon-rich oxide film comprises a SiOx film (1.5

    摘要翻译： 存储器件包括在衬底上的栅叠层。 栅极堆叠设置在源极和漏极之间。 栅极堆叠包括隧道膜，存储节点和控制氧化物膜。 控制氧化物膜的厚度大于或等于约5nm且小于或等于约30nm。 一种制造存储器件的方法，其包括在衬底上的栅极堆叠，其中所述栅极堆叠设置在源极和漏极之间，包括：顺序地形成隧道膜，第一富硅氧化物膜和控制氧化物膜 在所述衬底上，其中所述第一富氧氧化物膜包括SiO x薄膜（1.5

    Memory device and method for operating the same
    3.
    发明申请
    Memory device and method for operating the same 失效
    存储器件及其操作方法

    公开(公告)号：US20070211533A1

    公开(公告)日：2007-09-13

    申请号：US11704204

    申请日：2007-02-09

    申请人： Sang-Jin Park ,  Young-Soo Park ,  Sang-Min Shin ,  Young-Kwan Cha

    发明人： Sang-Jin Park ,  Young-Soo Park ,  Sang-Min Shin ,  Young-Kwan Cha

    IPC分类号： G11C16/04 ,  G11C11/34

    CPC分类号： G11C16/0416 ,  B82Y10/00 ,  G11C2216/06 ,  H01L29/42332 ,  H01L29/7881

    摘要： A memory device and method for operating the same are provided. The example method may be directed to a method of performing a memory operation on a memory device, and may include applying a negative voltage bias to the memory device during a programming operation of the memory device and applying a positive voltage bias to the memory device during an erasing operation of the memory device. The example memory device may include a substrate and a gate structure formed on the substrate, the gate structure exhibiting a faster flat band voltage shift under a negative voltage bias than under a positive voltage bias, the gate structure receiving a negative voltage bias during a programming of the memory device and receiving a positive voltage bias during an erasing operation of the memory device.

    摘要翻译： 提供了一种用于操作该存储器件的存储器件和方法。 示例性方法可以针对在存储器件上执行存储器操作的方法，并且可以包括在存储器件的编程操作期间向存储器件施加负电压偏压，并且在存储器件期间向存储器件施加正电压偏压 存储器件的擦除操作。 示例性存储器件可以包括衬底和形成在衬底上的栅极结构，栅极结构在负电压偏压下比在正电压偏压下表现出更快的平带电压偏移，栅极结构在编程期间接收负电压偏置 并且在存储器件的擦除操作期间接收正电压偏置。

    Semiconductor memory device having an alloy metal gate electrode and method of manufacturing the same
    4.
    发明申请
    Semiconductor memory device having an alloy metal gate electrode and method of manufacturing the same 审中-公开
    具有合金金属栅电极的半导体存储器件及其制造方法

    公开(公告)号：US20070190721A1

    公开(公告)日：2007-08-16

    申请号：US11655180

    申请日：2007-01-19

    申请人： Young-kwan Cha ,  Young-soo Park ,  Kwang-soo Seol ,  Sang-jin Park ,  Sang-min Shin

    发明人： Young-kwan Cha ,  Young-soo Park ,  Kwang-soo Seol ,  Sang-jin Park ,  Sang-min Shin

    IPC分类号： H01L21/336

    CPC分类号： H01L29/513 ,  H01L21/28088 ,  H01L29/40117 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/792

    摘要： A semiconductor memory device having an alloy gate electrode layer and method of manufacturing the same are provided. The semiconductor memory device may include a semiconductor substrate having a first impurity region and a second impurity region. The semiconductor memory device may include a gate structure formed on the semiconductor substrate and contacting the first and second impurity regions. The gate structure may include an alloy gate electrode layer formed of a first metal and a second metal. The first metal may be a noble metal. The second metal may include at least one of aluminum (Al) and titanium (Ti), gallium (Ga), indium (In), tin (Sb), thallium (Tl), bismuth (Bi) and lead (Pb).

    摘要翻译： 提供了具有合金栅电极层的半导体存储器件及其制造方法。 半导体存储器件可以包括具有第一杂质区和第二杂质区的半导体衬底。 半导体存储器件可以包括形成在半导体衬底上并与第一和第二杂质区接触的栅极结构。 栅极结构可以包括由第一金属和第二金属形成的合金栅极电极层。 第一种金属可能是贵金属。 第二金属可以包括铝（Al）和钛（Ti），镓（Ga），铟（In），锡（Sb），铊（Tl），铋（Bi）和铅（Pb）中的至少一种。

    BOTTOM GATE THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME
    7.
    发明申请
    BOTTOM GATE THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 失效
    底部薄膜薄膜晶体管及其制造方法

    公开(公告)号：US20100059750A1

    公开(公告)日：2010-03-11

    申请号：US12566106

    申请日：2009-09-24

    申请人： Hyuck LIM ,  Young-soo PARK ,  Wenxu XIANYU ,  Young-kwan CHA

    发明人： Hyuck LIM ,  Young-soo PARK ,  Wenxu XIANYU ,  Young-kwan CHA

    IPC分类号： H01L29/786

    CPC分类号： H01L29/78678 ,  H01L21/268 ,  H01L27/1285 ,  H01L29/66765 ,  H01L29/78609 ,  H01L29/78684 ,  H01L29/78696

    摘要： A method of manufacturing a bottom gate thin film transistor (“TFT”) in which a polycrystalline channel region having a large grain size is formed relatively simply and easily. The method of manufacturing a bottom gate thin film transistor includes forming a bottom gate electrode on a substrate, forming a gate insulating layer on the substrate to cover the bottom gate electrode, forming an amorphous semiconductor layer, an N-type semiconductor layer and an electrode layer on the gate insulating layer sequentially, etching an electrode region and an N-type semiconductor layer region formed on the bottom gate electrode sequentially to expose an amorphous semiconductor layer region, melting the amorphous semiconductor layer region using a laser annealing method, and crystallizing the melted amorphous semiconductor layer region to form a laterally grown polycrystalline channel region.

    摘要翻译： 相对简单且容易地形成具有大晶粒尺寸的多晶沟道区的底栅薄膜晶体管（“TFT”）的制造方法。 制造底栅极薄膜晶体管的方法包括在衬底上形成底栅电极，在衬底上形成栅极绝缘层以覆盖底栅电极，形成非晶半导体层，N型半导体层和电极 依次在栅极绝缘层上蚀刻形成在底栅电极上的电极区域和N型半导体层区域，以暴露非晶半导体层区域，使用激光退火法熔化非晶半导体层区域，并使 熔融的非晶半导体层区域以形成横向生长的多晶沟道区域。

    Nano-elastic memory device and method of manufacturing the same
    8.
    发明申请
    Nano-elastic memory device and method of manufacturing the same 失效
    纳米弹性记忆装置及其制造方法

    公开(公告)号：US20090068782A1

    公开(公告)日：2009-03-12

    申请号：US12289192

    申请日：2008-10-22

    申请人： Joo-han Chang ,  Dong-hun Kang ,  Young-kwan Cha ,  Wan-jun Park

    发明人： Joo-han Chang ,  Dong-hun Kang ,  Young-kwan Cha ,  Wan-jun Park

    IPC分类号： H01L21/00

    CPC分类号： H01L27/115 ,  B82Y10/00 ,  G11C13/025 ,  G11C23/00 ,  G11C2213/16 ,  Y10S977/742 ,  Y10S977/743 ,  Y10S977/842

    摘要： A nano-elastic memory device and a method of manufacturing the same. The nano-elastic memory device may include a substrate, a plurality of lower electrodes arranged in parallel on the substrate, a support unit formed of an insulating material to a desired or predetermined thickness on the substrate having cavities that expose the lower electrodes, a nano-elastic body extending perpendicular from a surface of the lower electrodes in the cavities, and a plurality of upper electrodes formed on the support unit and perpendicularly crossing the lower electrodes over the nano-elastic bodies.

    摘要翻译： 纳米弹性记忆装置及其制造方法。 纳米弹性存储装置可以包括基板，在基板上平行布置的多个下电极，在基板上具有期望或预定厚度的绝缘材料形成的支撑单元，该基板具有露出下电极的空腔， 在空腔中从下电极的表面垂直延伸的弹性体，以及形成在支撑单元上并与纳米弹性体上的下电极垂直交叉的多个上电极。

    Nano-elastic memory device and method of manufacturing the same
    9.
    发明授权
    Nano-elastic memory device and method of manufacturing the same 失效
    纳米弹性记忆装置及其制造方法

    公开(公告)号：US07453085B2

    公开(公告)日：2008-11-18

    申请号：US11505970

    申请日：2006-08-18

    申请人： Joo-han Chang ,  Dong-hun Kang ,  Young-kwan Cha ,  Wan-jun Park

    发明人： Joo-han Chang ,  Dong-hun Kang ,  Young-kwan Cha ,  Wan-jun Park

    IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L31/0352

    CPC分类号： H01L27/115 ,  B82Y10/00 ,  G11C13/025 ,  G11C23/00 ,  G11C2213/16 ,  Y10S977/742 ,  Y10S977/743 ,  Y10S977/842

    摘要： A nano-elastic memory device and a method of manufacturing the same. The nano-elastic memory device may include a substrate, a plurality of lower electrodes arranged in parallel on the substrate, a support unit formed of an insulating material to a desired or predetermined thickness on the substrate having cavities that expose the lower electrodes, a nano-elastic body extending perpendicular from a surface of the lower electrodes in the cavities, and a plurality of upper electrodes formed on the support unit and perpendicularly crossing the lower electrodes over the nano-elastic bodies.

    摘要翻译： 纳米弹性记忆装置及其制造方法。 纳米弹性存储装置可以包括基板，在基板上平行布置的多个下电极，在基板上具有期望或预定厚度的绝缘材料形成的支撑单元，该基板具有露出下电极的空腔， 在空腔中从下电极的表面垂直延伸的弹性体，以及形成在支撑单元上并与纳米弹性体上的下电极垂直交叉的多个上电极。