公开(公告)号：US08039349B2

公开(公告)日：2011-10-18

申请号：US12512814

申请日：2009-07-30

申请人： Michael J. Hargrove ,  Frank Scott Johnson ,  Scott Luning

发明人： Michael J. Hargrove ,  Frank Scott Johnson ,  Scott Luning

IPC分类号： H01L21/8234

CPC分类号： H01L21/26586 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7847 ,  H01L29/785

摘要： Embodiments of a method are provided for fabricating a non-planar semiconductor device including a substrate having a plurality of raised crystalline structures formed thereon. In one embodiment, the method includes the steps of amorphorizing a portion of each raised crystalline structure included within the plurality of raised crystalline structures, forming a sacrificial strain layer over the plurality of raised crystalline structures to apply stress to the amorphized portion of each raised crystalline structure, annealing the non-planar semiconductor device to recrystallize the amorphized portion of each raised crystalline structure in a stress-memorized state, and removing the sacrificial strain layer.

摘要翻译： 提供了一种用于制造包括其上形成有多个凸起的晶体结构的基板的非平面半导体器件的方法的实施例。 在一个实施方案中，该方法包括以下步骤：将包含在多个凸起的晶体结构内的每个凸起的晶体结构的一部分非晶化，在多个凸起的晶体结构上形成牺牲应变层，以将应力施加到每个凸起晶体的非晶化部分 结构，退火所述非平面半导体器件以使应力存储状态下的每个凸起晶体结构的非晶化部分重结晶，以及去除所述牺牲应变层。

公开(公告)号：US07977174B2

公开(公告)日：2011-07-12

申请号：US12480269

申请日：2009-06-08

申请人： Scott Luning ,  Frank Scott Johnson ,  Michael J. Hargrove

发明人： Scott Luning ,  Frank Scott Johnson ,  Michael J. Hargrove

IPC分类号： H01L21/00

CPC分类号： H01L29/7843 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

摘要： Methods for fabricating FinFET structures with stress-inducing source/drain-forming spacers and FinFET structures having such spacers are provided herein. In one embodiment, a method for fabricating a FinFET structure comprises fabricating a plurality of parallel fins overlying a semiconductor substrate. Each of the fins has sidewalls. A gate structure is fabricated overlying a portion of each of the fins. The gate structure has sidewalls and overlies channels within the fins. Stress-inducing sidewall spacers are formed about the sidewalls of the fins and the sidewalls of the gate structure. The stress-inducing sidewall spacers induce a stress within the channels. First conductivity-determining ions are implanted into the fins using the stress-inducing sidewall spacers and the gate structure as an implantation mask to form source and drain regions within the fins.

摘要翻译： 本文提供了制造具有应力诱导源极/漏极形成间隔物的FinFET结构和具有这种间隔物的FinFET结构的方法。 在一个实施例中，制造FinFET结构的方法包括制造覆盖半导体衬底的多个平行散热片。 每个翅片都有侧壁。 制造覆盖每个翅片的一部分的栅极结构。 栅极结构在翅片内具有侧壁并覆盖通道。 应力诱导侧壁间隔件围绕翅片的侧壁和门结构的侧壁形成。 应力诱导侧壁间隔物在通道内引起应力。 使用应力诱导侧壁间隔物和栅极结构作为注入掩模将第一导电率确定离子注入到鳍中，以在翅片内形成源区和漏区。

公开(公告)号：US20110266622A1

公开(公告)日：2011-11-03

申请号：US13180300

申请日：2011-07-11

申请人： Scott Luning ,  Frank Scott Johnson

发明人： Scott Luning ,  Frank Scott Johnson

IPC分类号： H01L29/786

CPC分类号： H01L29/7842 ,  H01L29/66795 ,  H01L29/785

摘要： A method of fabricating a semiconductor device is provided. The method forms a fin arrangement on a semiconductor substrate, the fin arrangement comprising one or more semiconductor fin structures. The method continues by forming a gate arrangement overlying the fin arrangement, where the gate arrangement includes one or more adjacent gate structures. The method proceeds by forming an outer spacer around sidewalls of each gate structure. The fin arrangement is then selectively etched, using the gate structure and the outer spacer(s) as an etch mask, resulting in one or more semiconductor fin sections underlying the gate structure(s). The method continues by forming a stress/strain inducing material adjacent sidewalls of the one or more semiconductor fin sections.

摘要翻译： 提供一种制造半导体器件的方法。 所述方法在半导体衬底上形成翅片布置，所述翅片布置包括一个或多个半导体翅片结构。 该方法通过形成覆盖鳍片布置的栅极布置继续，其中栅极布置包括一个或多个相邻栅极结构。 该方法通过在每个栅极结构的侧壁周围形成外部间隔来进行。 然后使用栅极结构和外部间隔物作为蚀刻掩模来选择性地蚀刻鳍片布置，从而导致栅极结构下面的一个或多个半导体鳍片部分。 该方法通过在一个或多个半导体鳍片部分的侧壁附近形成应力/应变诱导材料来继续。

公开(公告)号：US08030144B2

公开(公告)日：2011-10-04

申请号：US12576987

申请日：2009-10-09

申请人： Scott Luning ,  Frank Scott Johnson

发明人： Scott Luning ,  Frank Scott Johnson

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/338 ,  H01L21/336 ,  H01L21/3205

CPC分类号： H01L29/7842 ,  H01L29/66795 ,  H01L29/785

摘要： A method of fabricating a semiconductor device is provided. The method forms a fin arrangement on a semiconductor substrate, the fin arrangement comprising one or more semiconductor fin structures. The method continues by forming a gate arrangement overlying the fin arrangement, where the gate arrangement includes one or more adjacent gate structures. The method proceeds by forming an outer spacer around sidewalls of each gate structure. The fin arrangement is then selectively etched, using the gate structure and the outer spacer(s) as an etch mask, resulting in one or more semiconductor fin sections underlying the gate structure(s). The method continues by forming a stress/strain inducing material adjacent sidewalls of the one or more semiconductor fin sections.

摘要翻译： 提供一种制造半导体器件的方法。 所述方法在半导体衬底上形成翅片布置，所述翅片布置包括一个或多个半导体翅片结构。 该方法通过形成覆盖鳍片布置的栅极布置继续，其中栅极布置包括一个或多个相邻栅极结构。 该方法通过在每个栅极结构的侧壁周围形成外部间隔来进行。 然后使用栅极结构和外部间隔物作为蚀刻掩模来选择性地蚀刻鳍片布置，从而导致栅极结构下面的一个或多个半导体鳍片部分。 该方法通过在一个或多个半导体鳍片部分的侧壁附近形成应力/应变诱导材料来继续。

公开(公告)号：US08912603B2

公开(公告)日：2014-12-16

申请号：US13180300

申请日：2011-07-11

申请人： Scott Luning ,  Frank Scott Johnson

发明人： Scott Luning ,  Frank Scott Johnson

IPC分类号： H01L29/786 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/7842 ,  H01L29/66795 ,  H01L29/785

摘要： A method of fabricating a semiconductor device is provided. The method forms a fin arrangement on a semiconductor substrate, the fin arrangement comprising one or more semiconductor fin structures. The method continues by forming a gate arrangement overlying the fin arrangement, where the gate arrangement includes one or more adjacent gate structures. The method proceeds by forming an outer spacer around sidewalls of each gate structure. The fin arrangement is then selectively etched, using the gate structure and the outer spacer(s) as an etch mask, resulting in one or more semiconductor fin sections underlying the gate structure(s). The method continues by forming a stress/strain inducing material adjacent sidewalls of the one or more semiconductor fin sections.

摘要翻译： 提供一种制造半导体器件的方法。 所述方法在半导体衬底上形成翅片布置，所述翅片布置包括一个或多个半导体翅片结构。 该方法通过形成覆盖鳍片布置的栅极布置继续，其中栅极布置包括一个或多个相邻栅极结构。 该方法通过在每个栅极结构的侧壁周围形成外部间隔来进行。 然后使用栅极结构和外部间隔物作为蚀刻掩模来选择性地蚀刻鳍片布置，从而导致栅极结构下面的一个或多个半导体鳍片部分。 该方法通过在一个或多个半导体鳍片部分的侧壁附近形成应力/应变诱导材料来继续。

公开(公告)号：US07960287B2

公开(公告)日：2011-06-14

申请号：US12891365

申请日：2010-09-27

申请人： Frank Scott Johnson ,  Richard T. Schultz

发明人： Frank Scott Johnson ,  Richard T. Schultz

IPC分类号： H01L21/311

CPC分类号： H01L21/823431 ,  H01L29/66795 ,  H01L29/66818

摘要： Methods for fabricating FinFET structures having gate structures of different gate widths are provided. The methods include the formation of sidewall spacers of different thicknesses to define gate structures of the FinFET structures with different gate widths. The width of a sidewall spacer is defined by the height of the structure about which the sidewall spacer is formed, the thickness of the sidewall spacer material layer from which the spacer is formed, and the etch parameters used to etch the sidewall spacer material layer. By forming structures of varying height, forming the sidewall spacer material layer of varying thickness, or a combination of these, sidewall spacers of varying width can be fabricated and subsequently used as an etch mask so that gate structures of varying widths can be formed simultaneously.

摘要翻译： 提供了制造具有不同栅极宽度的栅极结构的FinFET结构的方法。 这些方法包括形成不同厚度的侧壁间隔物，以限定具有不同栅极宽度的FinFET结构的栅极结构。 侧壁间隔物的宽度由形成侧壁间隔物的结构的高度，形成间隔物的侧壁间隔材料层的厚度和用于蚀刻侧壁间隔物材料层的蚀刻参数限定。 通过形成不同高度的结构，形成不同厚度的侧壁间隔物材料层或这些的组合，可以制造不同宽度的侧壁间隔物，并随后用作蚀刻掩模，从而可以同时形成不同宽度的栅极结构。

公开(公告)号：US20090286375A1

公开(公告)日：2009-11-19

申请号：US12122885

申请日：2008-05-19

申请人： Mahalingam Nandakumar ,  Said Ghneim ,  Frank Scott Johnson

发明人： Mahalingam Nandakumar ,  Said Ghneim ,  Frank Scott Johnson

IPC分类号： H01L21/336

CPC分类号： H01L21/28247 ,  H01L29/6656

摘要： A method of forming sidewall spacers for a gate in a semiconductor device includes re-oxidizing/annealing silicon of the substrate and silicon of the gate after formation of the gate. The substrate is re-oxidized by performing an anneal in an inert atmosphere or ambient. The substrate may be re-oxidized/annealing after depositing an oxide layer covering the substrate and gate. Additionally, the substrate may be re-oxidized/annealing after forming the gate without depositing the oxide layer.

摘要翻译： 在半导体器件中形成用于栅极的侧壁间隔物的方法包括：在栅极形成之后，再次氧化/退火衬底的硅和栅极的硅。 通过在惰性气氛或环境中进行退火，使基板再次氧化。 在沉积覆盖衬底和栅极的氧化物层之后，衬底可以被再氧化/退火。 此外，可以在形成栅极之后再次氧化/退火衬底，而不沉积氧化物层。

公开(公告)号：US20090125865A1

公开(公告)日：2009-05-14

申请号：US11940270

申请日：2007-11-14

申请人： Thomas J. Aton ,  Carl A. Vickery ,  Frank Scott Johnson ,  James Walter Blatchford ,  Benjamen Michael Rathsack ,  Benjamin McKee

发明人： Thomas J. Aton ,  Carl A. Vickery ,  Frank Scott Johnson ,  James Walter Blatchford ,  Benjamen Michael Rathsack ,  Benjamin McKee

IPC分类号： G06F17/50 ,  H05K1/00

CPC分类号： G03F1/36

摘要： The present disclosure is directed a method for preparing photomask patterns. The method comprises receiving drawn pattern data for a design database. The drawn pattern data describes first device features and second device features, the second device features being associated with design specifications for providing a desired connectivity of the first device features to the second device features. At least a first plurality of the first device features have drawn patterns that will not result in sufficient coverage to effect the desired connectivity. Photomask patterns are formed for the first device features, wherein the photomask patterns for the first plurality of the first device features will result in the desired coverage. Integrated circuit devices formed using the principles of the present disclosure are also taught.

摘要翻译： 本公开涉及一种制备光掩模图案的方法。 该方法包括接收用于设计数据库的绘制图案数据。 所绘制的图案数据描述了第一设备特征和第二设备特征，第二设备特征与用于向第二设备特征提供第一设备特征的期望连接性的设计规范相关联。 至少第一多个第一设备特征具有不会导致足够的覆盖以实现期望的连接性的图形。 为第一器件特征形成光掩模图案，其中用于第一多个第一器件特征的光掩模图案将导致期望的覆盖。 还教导了使用本公开的原理形成的集成电路器件。

公开(公告)号：US08729609B2

公开(公告)日：2014-05-20

申请号：US12711022

申请日：2010-02-23

申请人： Frank Scott Johnson ,  Andreas Knorr

发明人： Frank Scott Johnson ,  Andreas Knorr

IPC分类号： H01L29/66

CPC分类号： H01L27/1207 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of an integrated circuit are provided. In one embodiment, the integrated circuit includes a substrate and a plurality of locally interconnected multi-gate transistors. The plurality of locally interconnected multi-gate transistors includes a continuous fin structure formed on the substrate and first and second multi-gate transistors formed on the substrate and including first and second fin segments of the continuous fin structure, respectively. The continuous fin structure electrically interconnects the first and second multi-gate transistors.

摘要翻译： 提供集成电路的实施例。 在一个实施例中，集成电路包括衬底和多个局部互连的多栅极晶体管。 多个本地互连的多栅极晶体管包括形成在衬底上的连续鳍结构，以及形成在衬底上的第一和第二多栅极晶体管，并且分别包括连续鳍结构的第一鳍片段和第二鳍片段。 连续翅片结构使第一和第二多栅极晶体管电连接。

公开(公告)号：US20130309838A1

公开(公告)日：2013-11-21

申请号：US13474443

申请日：2012-05-17

申请人： Andy C. Wei ,  Francis C. Tambwe ,  Frank Scott Johnson

发明人： Andy C. Wei ,  Francis C. Tambwe ,  Frank Scott Johnson

IPC分类号： H01L21/762

CPC分类号： H01L21/76229 ,  H01L21/3086 ,  H01L21/823821 ,  H01L29/6681

摘要： Methods are provided for fabricating FinFET integrated circuits on bulk semiconductor substrates. In accordance with one embodiment a patterned hard mask that defines locations of a regular array of a plurality of fins is formed overlying a semiconductor substrate. Portions of the patterned hard mask are removed using a cut mask to form a modified hard mask. The substrate is etched using the modified hard mask as an etch mask to form a plurality of fins extending upwardly from the substrate and separated by trenches. Selected ones of the plurality of fins are at least partially removed to form isolation regions and an insulating material is deposited to fill the trenches and to cover the at least partially removed selected ones of the plurality of fins.

摘要翻译： 提供了用于在体半导体衬底上制造FinFET集成电路的方法。 根据一个实施例，形成覆盖半导体衬底的限定多个翅片的规则阵列的位置的图案化硬掩模。 使用切割掩模去除图案化硬掩模的部分以形成修改的硬掩模。 使用改进的硬掩模作为蚀刻掩模蚀刻衬底，以形成从衬底向上延伸并由沟槽分离的多个鳍。 至少部分地去除多个翅片中的选定的翅片以形成隔离区域，并且沉积绝缘材料以填充沟槽并且覆盖多个翅片中的至少部分移除的选定翼片。