公开(公告)号：US06985030B2

公开(公告)日：2006-01-10

申请号：US10818791

申请日：2004-04-06

申请人： Yasuhide Shimizu ,  Hideyuki Katsuta ,  Yukitoshi Yamashita ,  Nobuhiko Yokoyama

发明人： Yasuhide Shimizu ,  Hideyuki Katsuta ,  Yukitoshi Yamashita ,  Nobuhiko Yokoyama

IPC分类号： H03F1/02 ,  H03M1/12

CPC分类号： H03F3/45192 ,  H03F3/45188 ,  H03F3/45771 ,  H03F2203/45651 ,  H03F2203/45652 ,  H03F2203/45696 ,  H03F2203/45702 ,  H03F2203/45726 ,  H03M1/148

摘要： A differential amplifier has an in-phase input terminal to which an input signal is applied through a first switching unit, an anti-phase input terminal to which a reference signal is applied through a second switching unit, and a third switching unit between the in-phase and anti-phase input terminals. The potential difference between the in-phase and anti-phase input terminals is differentially amplified by setting the first and second switching units to be on and the third switching unit to be off. Also, the in-phase and anti-phase input terminals are short-circuited to have a high impedance by setting the first and second switching units to be off and the third switching unit to be on.

摘要翻译： 差分放大器具有同相输入端子，通过第一开关单元向其施加输入信号，通过第二开关单元向其施加参考信号的反相输入端子，以及第三开关单元 相和反相输入端子。 通过将第一和第二开关单元设置为导通而使第三开关单元断开，同相和反相输入端子之间的电位差被差分放大。 此外，通过将第一和第二开关单元设置为关闭并且第三开关单元导通，同相和反相输入端子被短路以具有高阻抗。

公开(公告)号：US5083126A

公开(公告)日：1992-01-21

申请号：US427705

申请日：1989-10-27

申请人： Yoshihiro Komatsu ,  Youji Yoshii ,  Daisuke Murakami

发明人： Yoshihiro Komatsu ,  Youji Yoshii ,  Daisuke Murakami

IPC分类号： H03M1/14 ,  H03M1/36

CPC分类号： H03M1/148 ,  H03M1/365

摘要： Disclosed is a series-parallel type analog-to-digital converter having an analog signal first digitized through coarse quantization to thereby obtain a high-order converted code, and then, the quantization error of the high-order converted code digitized to thereby obtain a low-order converted code, in which it is adapted such that low-order converted codes are sequentially classified into three groups, and when a specific group is output as a redundancy code, a correction code for correcting the high-order converted code is output from the low-order encoder providing the converted code of that group.

摘要翻译： 公开了一种串并联型模数转换器，其具有通过粗量化首先数字化的模拟信号，从而获得高阶转换代码，然后将数字化的高阶转换代码的量化误差获得 低阶转换代码，其中适配使得低阶转换代码被顺序地分为三组，并且当特定组作为冗余码输出时，输出用于校正高阶转换代码的校正码 从提供该组的转换代码的低阶编码器。

公开(公告)号：US20170243044A1

公开(公告)日：2017-08-24

申请号：US15590060

申请日：2017-05-09

申请人： SHENZHEN HUIDING TECHNOLOGY CO., LTD.

发明人： BO TAN ,  CHANG ZHAN

IPC分类号： G06K9/00 ,  H03M1/36 ,  H03M1/00

CPC分类号： G06K9/001 ,  G06K9/0002 ,  G06K9/0008 ,  G06K9/6202 ,  H03M1/001 ,  H03M1/002 ,  H03M1/148 ,  H03M1/368 ,  H03M1/56

摘要： The present disclosure provides a signal conversion circuit and fingerprint identification system. The signal conversion circuit is configured to generate a first digital signal according to a first analog signal, and includes a comparator and counter. The comparator includes a first input terminal configured to receive the first analog signal, a second input terminal connected to a reference voltage generator and configured to receive a reference voltage, and an output terminal configured to output a second digital signal. The counter is connected to the output terminal, and is configured to generate a first digital signal. The signal conversion circuit according to the present disclosure has the advantages of simple circuit structure, small circuit area, low cost and low power consumption.

公开(公告)号：US5187483A

公开(公告)日：1993-02-16

申请号：US798617

申请日：1991-11-26

申请人： Masashi Yonemaru

发明人： Masashi Yonemaru

IPC分类号： H03M1/14 ,  H03M1/36

CPC分类号： H03M1/148 ,  H03M1/365

摘要： A serial-to-parallel type A/D converter includes a resistance array, a plurality of comparators for upper bits, a plurality of comparators for lower bits, an encoder for upper bits, an encoder for lower bits and an adder. The resistance array divides a predetermined reference voltage to generate upper reference voltages, and by dividing the step width of the upper reference voltage, generates lower reference voltages. The plurality of comparators for the upper bits compare the analog input signal with the upper reference voltages, and applies the result of comparison to the encoder for the upper bits. The encoder for the upper bits calculates an estimated value of the upper bits based on the result of comparison, and select second reference voltages in the range provided by adding .+-.1/2 LSB to 1LSB corresponding to the estimated value of the upper bits. The plurality of comparators for the lower bits calculate the lower bits and a correcting bit based on the selected second reference voltages. The adder adds the correcting bit to the estimated value of the upper bits to correct the estimated value.

摘要翻译： 串并转型A / D转换器包括电阻阵列，用于高位的多个比较器，用于低位的多个比较器，用于高位的编码器，用于低位的编码器和加法器。 电阻阵列划分预定的参考电压以产生上参考电压，并且通过划分上参考电压的步宽产生较低的参考电压。 用于高位的多个比较器将模拟输入信号与上参考电压进行比较，并将比较结果应用于高位的编码器。 用于高位的编码器基于比较结果计算高位的估计值，并且通过将与高位的估计值相对应的+/- 1 / LSB至+1LSB相加的范围中选择第二参考电压 。 用于低位的多个比较器基于所选择的第二参考电压计算低位和校正位。 加法器将校正位加到高位的估计值以校正估计值。

公开(公告)号：US4612531A

公开(公告)日：1986-09-16

申请号：US700866

申请日：1985-02-12

申请人： Andrew G. F. Dingwall ,  Victor Zazzu

发明人： Andrew G. F. Dingwall ,  Victor Zazzu

IPC分类号： H03M1/80 ,  H03M1/12 ,  H03M1/36 ,  H03M1/14

CPC分类号： H03M1/148 ,  H03M1/365

摘要： In an A/D converter, a resistive network for producing 2.sup.n different voltage steps. The resistive network includes a coarse relatively high impedance resistive string which is subdivided into 2.sup.x coarse segments. The resistive network also includes a fine relatively high impedance resistive network comprised of a fine resistive element per coarse segment. Each fine resistive element is then subdivided into 2.sup.(n-x) fine sub-segments. In determining the value of an input voltage being sensed, all the coarse segments are used to sense which coarse segments brackets the input voltage. However, only the fine segment in parallel with the "bracketing" coarse resistor is then coupled to comparator means to sense which fine sub-segment brackets the input voltage.

摘要翻译： 在A / D转换器中，用于产生2n个不同电压阶跃的电阻网络。 电阻网络包括粗略的相对高阻抗的电阻串，其被细分成两个粗的段。 电阻网络还包括一个精细的相对较高阻抗的电阻网络，每个粗细段都由精细的电阻元件组成。 然后将每个精细电阻元件细分为2（n-x）个细小分段。 在确定正在感测的输入电压的值时，所有粗略的部分用于感测哪些粗略部分支配输入电压。 然而，只有与“包围”粗电阻并联的精细分段然后被耦合到比较器装置以感测哪个精细子分段支架输入电压。

公开(公告)号：US20180069565A1

公开(公告)日：2018-03-08

申请号：US15697216

申请日：2017-09-06

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Norio SUGITA

IPC分类号： H03M1/34 ,  H03M1/18 ,  H03M1/12 ,  H03M1/14

CPC分类号： H03M1/34 ,  H03M1/0621 ,  H03M1/123 ,  H03M1/142 ,  H03M1/148 ,  H03M1/182

摘要： A semiconductor device includes an AD conversion unit that performs AD conversion on an input signal based on a reference voltage to be supplied, a reference voltage detection unit that detects the reference voltage supplied to the AD conversion unit, and a control unit that corrects a result of the AD conversion by the AD conversion unit in accordance with the reference voltage detected by the reference voltage detection unit. Thereby, AD conversion can be performed accurately even when a reference voltage varies.

公开(公告)号：US20040017305A1

公开(公告)日：2004-01-29

申请号：US10615391

申请日：2003-07-09

申请人： Matsushita Electric Industrial Co., Ltd.

发明人： Kenji Murata ,  Daisuke Nomasaki

IPC分类号： H03M001/66

CPC分类号： H03M1/148 ,  H03M1/362

摘要： The present invention provides a serial/parallel A/D converter which is capable of performing a high-speed and high-accuracy operation even in the case where an analog input voltage Vin greatly varies in a period between a previous sampling period in which the analog input voltage is held and the next sampling period, when converting the analog input voltage Vin input into a digital value. This serial/parallel A/D converter includes a lower-order reference voltage initializing circuit 8 for initializing a lower-order reference voltage to an initialization voltage Vrc 23. The initialization voltage Vrc 23 is generated as the lower-order reference voltage in an arbitrary period from the start of sampling of the analog input voltage until the start of a comparison operation for the lower-order reference voltage, the value of the lower-order reference voltage is changed from the value of the initialization voltage to a voltage value which is decided on the basis of higher-order code selection signals P0C-P3C from a higher-order code selecting circuit 14, and the value of the lower-order reference voltage which is decided on the basis of the higher-order code selection signals P0C-P3C is compared with the value of the analog input voltage.

公开(公告)号：US5870042A

公开(公告)日：1999-02-09

申请号：US734386

申请日：1996-10-17

申请人： Hiroshi Noda

发明人： Hiroshi Noda

IPC分类号： H03M1/10 ,  H03M1/14 ,  H03M1/38

CPC分类号： H03M1/109 ,  H03M1/148

摘要： When an upper reference voltage is erroneously reduced below a normal value in a subranging A-D converter, a resistance block of a ladder resistance having a voltage lower than a proper one is selected and a lower reference voltage is necessarily reduced below an analog input voltage, so that all outputs of lower bits go high. Namely, a region (B1) where a current flowing to a comparator becomes constant without depending on the value of an analog input voltage (Vin) appears. Presence of abnormality can be determined by detecting this. Thus, a functional test or a static linearity test of an A-D converter cell is made while remarkably reducing the number of external test terminals.

摘要翻译： 当在辅助AD转换器中上限参考电压被错误地降低到正常值以下时，选择具有低于适当电压的梯形电阻的电阻块，并且下参考电压必然降低到低于模拟输入电压，因此 低位的所有输出变高。 即，出现流过比较器的电流变得恒定的区域（B1），而不依赖于模拟输入电压（Vin）的值。 通过检测可以确定是否存在异常。 因此，在显着减少外部测试端子的数量的同时，进行A-D转换器单元的功能测试或静态线性测试。

公开(公告)号：US5696510A

公开(公告)日：1997-12-09

申请号：US443517

申请日：1995-05-18

申请人： Frederic Paillardet ,  Francis Dell'Ova ,  Bruno Bonhoure

发明人： Frederic Paillardet ,  Francis Dell'Ova ,  Bruno Bonhoure

IPC分类号： H03M1/14 ,  H03M1/12 ,  H03M1/36 ,  H03M1/34

CPC分类号： H03M1/1215 ,  H03M1/148 ,  H03M1/365

摘要： The disclosure is an analog-to-digital converter of half-flash type providing for the multiplexing of two analog input signals and therefore requiring only one converter module. It includes a coarse comparator block used to determine the most significant bits of the converted signals and also determining the voltage range for two fine comparator blocks that determine the least significant bits of the converted signals, wherein each of the input signals is connected to a fine comparator block and said coarse comparator block compares alternatively the first and second input signals with a reference voltage. The analog-to-digital converter can be advantageously used for processing television signals.

摘要翻译： 本公开是半闪存型的模数转换器，其提供两个模拟输入信号的复用，因此仅需要一个转换器模块。 它包括用于确定转换信号的最高有效位的粗略比较器块，并且还确定确定转换信号的最低有效位的两个精细比较器块的电压范围，其中每个输入信号被连接到一个精细 比较器块和所述粗略比较器块将第一和第二输入信号与参考电压进行比较。 模拟 - 数字转换器可以有利地用于处理电视信号。

公开(公告)号：US5923277A

公开(公告)日：1999-07-13

申请号：US878608

申请日：1997-06-19

申请人： Hitoshi Takeda

发明人： Hitoshi Takeda

IPC分类号： H03M1/14 ,  H03M1/36

CPC分类号： H03M1/148 ,  H03M1/365

摘要： A series-parallel A/D converter having a plurality of reference resistors, a first comparator section, a second comparator section, groups of switches, and lower-reference voltage lines. The reference resistors divide a full-scale voltage, generating different reference voltages. They are connected in series, forming blocks of resistors. The first comparator section compares an input voltage with upper reference voltages and selects one of the blocks of resistors in accordance with the result of comparison. The groups of switches applies the voltages at the nodes of the reference resistors of the selected block, to the lower-reference voltage lines. When the block BL0 is selected, voltages Vr0 and Vr8 are applied to the lower-reference voltage lines L0 and L8, respectively. When the block BL1 is selected, voltages Vr16 and Vr8 are applied to the lines L0 and L8, respectively. That is, the voltage applied through the line L8 remains unchanged, whichever block of resistors is selected.

摘要翻译： 具有多个参考电阻器的串并联A / D转换器，第一比较器部分，第二比较器部分，开关组和下参考电压线。 参考电阻划分满量程电压，产生不同的参考电压。 它们串联连接，形成电阻块。 第一比较器部分将输入电压与上参考电压进行比较，并根据比较结果选择电阻块中的一个。 开关组将所选块的参考电阻的节点处的电压施加到下参考电压线。 当选择块BL0时，电压Vr0和Vr8分别施加到下参考电压线L0和L8。 当选择块BL1时，电压Vr16和Vr8分别施加到线路L0和L8。 也就是说，通过线路L8施加的电压保持不变，无论哪个电阻块被选择。