Pipeline processing system and information processing apparatus
    3.
    发明授权
    Pipeline processing system and information processing apparatus 失效
    管道处理系统和信息处理设备

    公开(公告)号:US07689103B2

    公开(公告)日:2010-03-30

    申请号:US10928430

    申请日:2004-08-27

    申请人: Tsuneo Hayashi

    发明人: Tsuneo Hayashi

    IPC分类号: H04N7/26 H04N7/00

    摘要: A pipeline processing system capable of high speed operation and capable of realizing a reduction of power consumption and an information processing apparatus to which this is applied, wherein a decoder/encoder circuit accesses a first memory and a second memory in parallel in accordance with status information at decoding processing to perform decoding processing, stores the data after processing in a tracking memory, then transfers the data stored in the tracking memory to a host apparatus according to a request from the host apparatus, while writes the user data transferred in unit of blocks from the host apparatus in a third memory serving as a tracking buffer to start the encoder processing in the case of the encoding processing, accesses a plurality of memories in parallel in accordance with the status information to perform the encoding processing, and outputs the same to a clock generation circuit.

    摘要翻译: 一种能够高速运行并且能够实现降低功耗的流水线处理系统以及应用于其的信息处理装置,其中解码器/编码器电路根据状态信息并行地访问第一存储器和第二存储器 在执行解码处理的解码处理中,将处理后的数据存储在跟踪存储器中,然后根据主机装置的请求将存储在跟踪存储器中的数据传送到主机装置,同时以块为单位传送的用户数据 在作为跟踪缓冲器的第三存储器中的主机装置中,在编码处理的情况下开始编码器处理,根据状态信息并行访问多个存储器以执行编码处理,并将其输出到 时钟发生电路。

    Pipeline processing system and information processing apparatus
    8.
    发明授权
    Pipeline processing system and information processing apparatus 失效
    管道处理系统和信息处理设备

    公开(公告)号:US07539859B2

    公开(公告)日:2009-05-26

    申请号:US10902964

    申请日:2004-07-30

    申请人: Tsuneo Hayashi

    发明人: Tsuneo Hayashi

    IPC分类号: G06F9/00

    CPC分类号: G11B20/00086 H04N5/85

    摘要: A pipeline processing system and an information processing apparatus not malfunctioning even if there is a pipeline stage in which data is not correctly written, including a plurality of processing circuits for applying predetermined processing to a plurality of data blocks; memories accessed by any circuit of a plurality of processing circuits, encryptor for encrypting the data based on key information set for each series of pipeline processings continuously processed when storing processing results of the circuits in the memories; and decoders for decoding data based on set information used for the encrypting when reading the data encrypted and stored in the memories.

    摘要翻译: 即使存在没有正确写入数据的流水线阶段的流水线处理系统和信息处理装置也不发生故障,包括用于对多个数据块进行预定处理的多个处理电路; 由多个处理电路的任何电路访问的存储器,用于在将电路的处理结果存储在存储器中时基于连续处理的每一系列管线处理设置的密钥信息来加密数据的加密器; 以及用于在读取加密和存储在存储器中的数据时基于用于加密的设置信息来解码数据的解码器。

    Pipeline processing system and information processing apparatus
    9.
    发明申请
    Pipeline processing system and information processing apparatus 审中-公开
    管道处理系统和信息处理设备

    公开(公告)号:US20050097293A1

    公开(公告)日:2005-05-05

    申请号:US10928398

    申请日:2004-08-27

    申请人: Tsuneo Hayashi

    发明人: Tsuneo Hayashi

    摘要: A pipeline processing system capable of high speed operation and capable of realizing a reduction of power consumption and an information processing apparatus to which this is applied, wherein a decoder/encoder circuit accesses a first memory and a second memory in parallel in accordance with status information at decoding processing to perform decoding processing, stores the data after processing in a tracking memory, then transfers the data stored in the tracking memory to a host apparatus according to a request from the host apparatus, while writes the user data transferred in unit of blocks from the host apparatus in a third memory serving as a tracking buffer to start the encoder processing in the case of the encoding processing, accesses a plurality of memories in parallel in accordance with the status information to perform the encoding processing, and outputs the same to a clock generation circuit.

    摘要翻译: 一种能够高速运行并且能够实现降低功耗的流水线处理系统以及应用于其的信息处理装置,其中解码器/编码器电路根据状态信息并行地访问第一存储器和第二存储器 在执行解码处理的解码处理中,将处理后的数据存储在跟踪存储器中,然后根据主机装置的请求将存储在跟踪存储器中的数据传送到主机装置,同时以块为单位传送的用户数据 在作为跟踪缓冲器的第三存储器中的主机装置中,在编码处理的情况下开始编码器处理,根据状态信息并行访问多个存储器以执行编码处理,并将其输出到 时钟发生电路。

    INFORMATION PROCESSING APPARATUS AND METHOD, IMAGE PROVIDING SYSTEM AND IMAGE PROVIDING METHOD, AND PROGRAM
    10.
    发明申请
    INFORMATION PROCESSING APPARATUS AND METHOD, IMAGE PROVIDING SYSTEM AND IMAGE PROVIDING METHOD, AND PROGRAM 有权
    信息处理装置和方法,图像提供系统和图像提供方法及程序

    公开(公告)号:US20120251014A1

    公开(公告)日:2012-10-04

    申请号:US13423655

    申请日:2012-03-19

    IPC分类号: G06K9/36

    摘要: An information processing apparatus includes a two-dimensional orthogonal transform coding data acquisition unit for sequentially acquiring two-dimensional orthogonal transform coding data acquired by transforming three-dimensional orthogonal transform coding data generated from a plurality of images, a two-dimensional orthogonal transform coefficient data generation unit for generating a plurality of pieces of two-dimensional orthogonal transform coefficient data using the plurality of pieces of acquired two-dimensional orthogonal transform coding data, and a three-dimensional transformation unit for encoding three-dimensional orthogonal transform coefficient data acquired by transforming the plurality of pieces of generated two-dimensional orthogonal transform coefficient data.

    摘要翻译: 一种信息处理装置,包括:二维正交变换编码数据取得部,其将通过变换从多个图像生成的三维正交变换编码数据变换得到的二维正交变换编码数据,二维正交变换系数数据 生成单元,用于使用所述多个获取的二维正交变换编码数据生成多个二维正交变换系数数据;以及三维变换单元,用于对通过变换获取的三维正交变换系数数据进行编码 多个生成的二维正交变换系数数据。