Abstract:
A display device with high luminance is provided. A pixel includes a light-emitting device, a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, and a second capacitor. One electrode of the light-emitting device is electrically connected to one of a source and a drain of the first transistor. A gate of the first transistor is electrically connected to one electrode of the first capacitor and one of a source and a drain of the second transistor. The other of the source and the drain of the first transistor is electrically connected to one electrode of the second capacitor. One electrode of the second capacitor is electrically connected to a first wiring having a function of supplying a first potential. The other electrode of the second capacitor is electrically connected to the other electrode of the first capacitor, one of a source and a drain of the third transistor, and one of a source and a drain of the fourth transistor.
Abstract:
An object is to provide an electronic device capable of recognizing a user's facial feature accurately. A glasses-type electronic device includes a first optical component, a second optical component, a frame, an imaging device, a feature extraction unit, and an emotion estimation unit. The frame is in contact with a side surface of the first optical component and a side surface of the second optical component. The imaging device is in contact with the frame and has a function of detecting part of a user's face. The feature extraction unit has a function of extracting a feature of the user's face from the detected part of the user's face. The emotion estimation unit has a function of estimating information on the user from the extracted feature.
Abstract:
A semiconductor device in which the accuracy of arithmetic operation is increased by correction of the threshold voltage of a transistor can be provided. The semiconductor device includes first and second current supply circuits, and the second current supply circuit has the same configuration as the first current supply circuit. The first current supply circuit includes first and second transistors, a first capacitor, and first to third nodes. A first terminal of the first transistor is electrically connected to the first node, and a back gate of the first transistor is electrically connected to a first terminal of the second transistor and a first terminal of the first capacitor. A gate of the first transistor is electrically connected to the second node, and a second terminal of the first capacitor is electrically connected to a second terminal of the first transistor. The first node of the first current supply circuit is electrically connected to a second node of each of the first and second current supply circuits. The threshold voltage of the first transistor is corrected by writing a correction voltage to the back gate of the first transistor.
Abstract:
A novel semiconductor device is provided. The semiconductor device includes a programmable logic device including a programmable logic element, a control circuit, and a detection circuit. The programmable logic device includes a plurality of contexts. The control circuit is configured to control selection of the contexts. The detection circuit is configured to output a signal corresponding to the amount of radiation. The control circuit is configured to switch between a first mode and a second mode in accordance with the signal corresponding to the amount of radiation. The first mode is a mode in which the programmable logic device performs processing by a multi-context method, and the second mode is a mode in which the programmable logic device performs processing using a majority signal of signals output from the logic element multiplexed by the plurality of contexts.
Abstract:
A novel semiconductor device, a semiconductor device with low power consumption, a semiconductor device capable of displaying a high-quality image, or a semiconductor device with a small area is provided. The semiconductor device includes an image processing portion and a driver circuit. The image processing portion includes a processor and a correction circuit. The correction circuit includes a PLD. The correction circuit is capable of correcting data input from the processor using the PLD. The processor is capable of outputting data corrected by the correction circuit to the driver circuit as a video signal. The PLD is capable of executing first gamma correction by input of first configuration data. The PLD is capable of executing second gamma correction by input of second configuration data. The content of the first gamma correction is different from that of the second gamma correction.
Abstract:
A semiconductor device in which operation delay due to stop and restart of the supply of a power supply potential is suppressed is provided. Potentials corresponding to data held in first and second nodes while the supply of a power supply potential is continued are backed up in third and fourth nodes while the supply of the power supply potential is stopped. After the supply of the power supply potential is restarted, data are restored to the first and second nodes by utilizing a change in channel resistance of a transistor whose gate is electrically connected to the third or fourth node. Note that shoot-through current is suppressed at the time of data restoration by electrically disconnecting the power supply potential and the first or second node from each other.
Abstract:
A novel transmissive imaging panel, a novel imaging panel with a display function, or a novel imaging device is provided. The imaging panel that includes a plurality of windows or pixels arranged in matrix, a photoelectric conversion element extending between the plurality of windows or pixels, and a sensor circuit supplied with a signal from the photoelectric conversion element has been devised.
Abstract:
An imaging device that can obtain imaging data corresponding to high-resolution images in a short period of time is provided. The imaging device includes a pixel including a photoelectric conversion element and n (n is an integer more than 2 inclusive) retention circuits. The photoelectric conversion element and the n retention circuits are stacked. One electrode of the photoelectric conversion element is electrically connected to the first to n-th retention circuits. The retention circuits include OS transistors with an extremely low off-state current feature, and can retain imaging data for a long time. In the first to n-th periods, the imaging device obtains the first to n-th imaging data and retains it in the first to n-th retention circuits. Then, the first to n-th imaging data retained in the first to n-th retention circuits are read out. The read imaging data is output outside the imaging data through AD conversion.
Abstract:
To provide a semiconductor device that can reduce power consumption and retain data for a long time and a memory device including the semiconductor device. The semiconductor device includes a word line divider, a memory cell, a first wiring, and a second wiring. The word line divider is electrically connected to the first wiring and the second wiring. The memory cell includes a first transistor with a dual-gate structure. A first gate of the first transistor is electrically connected to the first wiring, and a second gate of the first transistor is electrically connected to the second wiring. The word line divider supplies a high-level potential or a low-level potential to the first wiring and supplies a predetermined potential to the second wiring, whereby a threshold voltage of the first transistor is changed. With such a configuration, a semiconductor device that can reduce power consumption and retain data for a long time is driven.
Abstract:
To provide a semiconductor device that can reduce power consumption and retain data for a long time and a memory device including the semiconductor device. The semiconductor device includes a word line divider, a memory cell, a first wiring, and a second wiring. The word line divider is electrically connected to the first wiring and the second wiring. The memory cell includes a first transistor with a dual-gate structure. A first gate of the first transistor is electrically connected to the first wiring, and a second gate of the first transistor is electrically connected to the second wiring. The word line divider supplies a high-level potential or a low-level potential to the first wiring and supplies a predetermined potential to the second wiring, whereby a threshold voltage of the first transistor is changed. With such a configuration, a semiconductor device that can reduce power consumption and retain data for a long time is driven.