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    Thin film transistor array panel and manufacturing method thereof
    2.
    发明授权
    Thin film transistor array panel and manufacturing method thereof 有权
    薄膜晶体管阵列面板及其制造方法

    公开(公告)号：US08519393B2

    公开(公告)日：2013-08-27

    申请号：US12823043

    申请日：2010-06-24

    申请人： Tae-Young Choi ,  Hi-Kuk Lee ,  Bo-Sung Kim ,  Young-Min Kim ,  Seung-Hwan Cho ,  Young-Soo Yoon ,  Yeon-Taek Jeong ,  Seon-Pil Jang

    发明人： Tae-Young Choi ,  Hi-Kuk Lee ,  Bo-Sung Kim ,  Young-Min Kim ,  Seung-Hwan Cho ,  Young-Soo Yoon ,  Yeon-Taek Jeong ,  Seon-Pil Jang

    IPC分类号： H01L27/146 ,  H01L29/786

    CPC分类号： H01L29/66765 ,  H01L21/02554 ,  H01L21/02565 ,  H01L27/1225 ,  H01L29/7869

    摘要： A thin film transistor array panel according to an exemplary embodiment of the present invention includes: a gate electrode disposed on an insulation substrate; a gate insulating layer disposed on the gate electrode; a semiconductor disposed on the gate insulating layer; an etching stop layer disposed on the semiconductor; an insulating layer disposed on the gate insulating layer; and a source electrode and a drain electrode overlapping the semiconductor. The semiconductor and the gate insulating layer have a first portion on which the etching stop layer and the insulating layer are disposed, and a second portion on which etching stop layer and the insulating layer are not disposed. The source electrode and the drain electrode are disposed on the second portion of the semiconductor and the gate insulating layer.

    摘要翻译： 根据本发明的示例性实施例的薄膜晶体管阵列面板包括：栅极，设置在绝缘基板上; 设置在栅电极上的栅极绝缘层; 设置在所述栅极绝缘层上的半导体; 设置在所述半导体上的蚀刻停止层; 设置在所述栅极绝缘层上的绝缘层; 以及与半导体重叠的源电极和漏电极。 半导体和栅极绝缘层具有其上设置有蚀刻停止层和绝缘层的第一部分，以及不设置蚀刻停止层和绝缘层的第二部分。 源电极和漏极设置在半导体的第二部分和栅极绝缘层上。

    THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF
    4.
    发明申请
    THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF 有权
    薄膜晶体管阵列及其制造方法

    公开(公告)号：US20110140094A1

    公开(公告)日：2011-06-16

    申请号：US12823043

    申请日：2010-06-24

    申请人： Tae-Young Choi ,  Hi-Kuk Lee ,  Bo-Sung Kim ,  Young-Min Kim ,  Seung-Hwan Cho ,  Young-Soo Yoon ,  Yeon-Taek Jeong ,  Seon-Pil Jang

    发明人： Tae-Young Choi ,  Hi-Kuk Lee ,  Bo-Sung Kim ,  Young-Min Kim ,  Seung-Hwan Cho ,  Young-Soo Yoon ,  Yeon-Taek Jeong ,  Seon-Pil Jang

    IPC分类号： H01L27/12 ,  H01L21/84 ,  H01L21/34 ,  H01L29/12

    CPC分类号： H01L29/66765 ,  H01L21/02554 ,  H01L21/02565 ,  H01L27/1225 ,  H01L29/7869

    摘要： A thin film transistor array panel according to an exemplary embodiment of the present invention includes: a gate electrode disposed on an insulation substrate; a gate insulating layer disposed on the gate electrode; a semiconductor disposed on the gate insulating layer; an etching stop layer disposed on the semiconductor; an insulating layer disposed on the gate insulating layer; and a source electrode and a drain electrode overlapping the semiconductor. The semiconductor and the gate insulating layer have a first portion on which the etching stop layer and the insulating layer are disposed, and a second portion on which etching stop layer and the insulating layer are not disposed. The source electrode and the drain electrode are disposed on the second portion of the semiconductor and the gate insulating layer

    摘要翻译： 根据本发明的示例性实施例的薄膜晶体管阵列面板包括：栅极，设置在绝缘基板上; 设置在栅电极上的栅极绝缘层; 设置在所述栅极绝缘层上的半导体; 设置在所述半导体上的蚀刻停止层; 设置在所述栅极绝缘层上的绝缘层; 以及与半导体重叠的源电极和漏电极。 半导体和栅极绝缘层具有其上设置有蚀刻停止层和绝缘层的第一部分，以及不设置蚀刻停止层和绝缘层的第二部分。 源电极和漏极设置在半导体的第二部分和栅极绝缘层上

    Display substrate and method of manufacturing the same
    6.
    发明授权
    Display substrate and method of manufacturing the same 有权
    显示基板及其制造方法

    公开(公告)号：US08367444B2

    公开(公告)日：2013-02-05

    申请号：US12902761

    申请日：2010-10-12

    申请人： Young-Min Kim ,  Bo-Sung Kim ,  Seon-Pil Jang ,  Seung-Hwan Cho ,  Kang-Moon Jo

    发明人： Young-Min Kim ,  Bo-Sung Kim ,  Seon-Pil Jang ,  Seung-Hwan Cho ,  Kang-Moon Jo

    IPC分类号： H01L21/02

    CPC分类号： H01L29/78606 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/1288

    摘要： A display substrate includes a gate line, a gate insulation layer, a data line, a switching element, a protection insulation layer, a gate pad portion and a data pad portion. The gate insulation layer is disposed on the gate line. The switching element is connected to the gate line and the data line. The protection insulation layer is disposed on the switching element. The gate pad portion includes a first gate pad electrode which makes contact with an end portion of the gate line through a first hole formed through the gate insulation layer, and a second gate pad electrode which makes contact with the first gate pad electrode through a second hole formed through the protection insulation layer. The data pad portion includes a data pad electrode which makes contact with an end portion of the data line through a third hole formed through the protection insulation layer.

    摘要翻译： 显示基板包括栅极线，栅极绝缘层，数据线，开关元件，保护绝缘层，栅极焊盘部分和数据焊盘部分。 栅极绝缘层设置在栅极线上。 开关元件连接到栅极线和数据线。 保护绝缘层设置在开关元件上。 栅极焊盘部分包括通过形成在栅极绝缘层上的第一孔与栅极线的端部接触的第一栅极焊盘电极和通过第二栅极焊盘电极与第一栅极焊盘电极接触的第二栅极焊盘电极 孔通过保护层形成。 数据焊盘部分包括通过形成在保护绝缘层上的第三孔与数据线的端部接触的数据焊盘电极。

    Thin film transistor array panel and manufacture thereof
    7.
    发明授权
    Thin film transistor array panel and manufacture thereof 有权
    薄膜晶体管阵列及其制造

    公开(公告)号：US07977144B2

    公开(公告)日：2011-07-12

    申请号：US12772845

    申请日：2010-05-03

    申请人： Seung-Hwan Cho ,  Bo-Sung Kim ,  Keun-Kyu Song ,  Tae-Young Choi ,  Jung-Hun Noh

    发明人： Seung-Hwan Cho ,  Bo-Sung Kim ,  Keun-Kyu Song ,  Tae-Young Choi ,  Jung-Hun Noh

    IPC分类号： H01L21/00

    CPC分类号： H01L51/0545 ,  H01L27/283 ,  H01L27/3244 ,  H01L51/0021

    摘要： A method for a thin film transistor array panel includes forming a gate line and a pixel electrode on a substrate, forming a gate insulating layer covering the gate line, forming a data line including a source electrode and a drain electrode on the gate insulating layer, forming an interlayer insulating layer covering the data line and the drain electrode on the gate insulating layer, forming a first opening in the interlayer insulating layer, forming an organic semiconductor in the first opening, forming a passivation layer on the organic semiconductor and the interlayer insulating layer, and forming a second opening in the interlayer insulating layer to expose the pixel electrode.

    摘要翻译： 一种薄膜晶体管阵列面板的制造方法，在基板上形成栅极线和像素电极，形成覆盖栅极线的栅极绝缘层，在栅极绝缘层上形成包括源电极和漏极的数据线， 在所述栅绝缘层上形成覆盖所述数据线和所述漏电极的层间绝缘层，在所述层间绝缘层中形成第一开口，在所述第一开口中形成有机半导体，在所述有机半导体上形成钝化层， 并且在所述层间绝缘层中形成第二开口以使所述像素电极露出。

    THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF
    8.
    发明申请
    THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF 有权
    薄膜晶体管阵列及其制造方法

    公开(公告)号：US20080078993A1

    公开(公告)日：2008-04-03

    申请号：US11864581

    申请日：2007-09-28

    申请人： Seung-Hwan CHO ,  Bo-Sung Kim ,  Keun-Kyu Song ,  Tae-Young Choi ,  Min-Ho Yoon ,  Jung-Hun Noh

    发明人： Seung-Hwan CHO ,  Bo-Sung Kim ,  Keun-Kyu Song ,  Tae-Young Choi ,  Min-Ho Yoon ,  Jung-Hun Noh

    IPC分类号： H01L51/10 ,  H01L51/40

    CPC分类号： H01L51/0541 ,  H01L51/0023 ,  H01L51/102

    摘要： A manufacturing method for a thin film transistor array panel including forming a gate electrode, forming an insulating layer on the gate electrode, sequentially forming a lower conducting layer and a upper conducting layer on the insulating layer, etching the upper conducting layer to form a first source electrode and a first drain electrode, etching the lower conducting layer to form the second source electrode and the second drain electrode, over-etching the second source electrode and the second drain electrode, and forming an organic semiconductor between the second source electrode and the second drain electrode.

    摘要翻译： 一种薄膜晶体管阵列板的制造方法，包括形成栅电极，在栅电极上形成绝缘层，在绝缘层上依次形成下导电层和上导电层，蚀刻上导电层以形成第一 源电极和第一漏电极，蚀刻下导电层以形成第二源电极和第二漏电极，过蚀刻第二源电极和第二漏电极，以及在第二源电极和第二漏电极之间形成有机半导体 第二漏电极。

    Making organic thin film transistor array panels
    9.
    发明申请
    Making organic thin film transistor array panels 有权
    制造有机薄膜晶体管阵列面板

    公开(公告)号：US20080012008A1

    公开(公告)日：2008-01-17

    申请号：US11634413

    申请日：2006-12-05

    申请人： Keun-Kyu Song ,  Bo-Sung Kim ,  Seung-Hwan Cho

    发明人： Keun-Kyu Song ,  Bo-Sung Kim ,  Seung-Hwan Cho

    IPC分类号： H01L29/08 ,  H01L21/84

    CPC分类号： H01L51/0021 ,  H01L27/283 ,  H01L51/0545 ,  H01L51/102

    摘要： An organic thin film transistor (OTFT) array panel for a display device includes a gate line and a pixel electrode formed on a substrate, the gate line and pixel electrode each having a first conductive layer including a transparent conductive oxide and a second conductive layer including a metal, a data line crossing the gate line and including a source electrode, a drain electrode facing the source electrode and connected with the pixel electrode, and an organic semiconductor in contact with the source electrode and the drain electrode.

    摘要翻译： 用于显示装置的有机薄膜晶体管（OTFT）阵列面板包括形成在基板上的栅极线和像素电极，栅线和像素电极各自具有包括透明导电氧化物的第一导电层和包括第 金属，与栅极线交叉的数据线，包括源电极，面对源极的漏电极，与像素电极连接，以及与源电极和漏极接触的有机半导体。

    Thin film transistor array panel and manufacturing method thereof
    10.
    发明授权
    Thin film transistor array panel and manufacturing method thereof 有权
    薄膜晶体管阵列面板及其制造方法

    公开(公告)号：US08252626B2

    公开(公告)日：2012-08-28

    申请号：US12820024

    申请日：2010-06-21

    申请人： Seung-Hwan Cho ,  Bo-Sung Kim ,  Keun-Kyu Song ,  Tae-Young Choi ,  Min-Ho Yoon ,  Jung-Hun Noh

    发明人： Seung-Hwan Cho ,  Bo-Sung Kim ,  Keun-Kyu Song ,  Tae-Young Choi ,  Min-Ho Yoon ,  Jung-Hun Noh

    IPC分类号： H01L51/40

    CPC分类号： H01L51/0541 ,  H01L51/0023 ,  H01L51/102

    摘要： A manufacturing method for a thin film transistor array panel including forming a gate electrode, forming an insulating layer on the gate electrode, sequentially forming a lower conducting layer and a upper conducting layer on the insulating layer, etching the upper conducting layer to form a first source electrode and a first drain electrode, etching the lower conducting layer to form the second source electrode and the second drain electrode, over-etching the second source electrode and the second drain electrode, and forming an organic semiconductor between the second source electrode and the second drain electrode.

    摘要翻译： 一种薄膜晶体管阵列板的制造方法，包括形成栅电极，在栅电极上形成绝缘层，在绝缘层上依次形成下导电层和上导电层，蚀刻上导电层以形成第一 源电极和第一漏电极，蚀刻下导电层以形成第二源电极和第二漏电极，过蚀刻第二源电极和第二漏电极，以及在第二源电极和第二漏电极之间形成有机半导体 第二漏电极。