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22 条记录 (耗时 0.021 秒)

    Thin film thermoelectric module
    2.
    发明申请
    Thin film thermoelectric module 审中-公开
    薄膜热电模块

    公开(公告)号：US20060048807A1

    公开(公告)日：2006-03-09

    申请号：US11223284

    申请日：2005-09-08

    申请人： Seung-Min Lee ,  Jeong-Il Kye

    发明人： Seung-Min Lee ,  Jeong-Il Kye

    IPC分类号： H01L35/30 ,  H01L35/28

    CPC分类号： H01L35/32

    摘要： Disclosed herein is a thin film thermoelectric module. the module includes high and low temperature part module substrates, unit thermoelectric devices, and lead wires. The high and low temperature part module substrates are arranged to face each other. The unit thermoelectric devices are located between the modules to transfer heat between the modules. The lead wires are connected to the electrodes of the unit thermoelectric devices. Each of the unit thermoelectric devices includes a pair of lower and upper substrates, electrodes, and a thermoelectric material. The pair of lower and upper substrates are arranged to face each other. The electrodes are formed on the upper surface of the lower substrate and the lower surface of the upper substrate. The thermoelectric material is disposed between the electrodes.

    摘要翻译： 这里公开了一种薄膜热电模块。 该模块包括高低温部件模块基板，单元热电装置和引线。 高低温部件模块基板被布置成彼此面对。 单元热电装置位于模块之间，以在模块之间传递热量。 引线连接到单元热电装置的电极。 每个单元热电装置包括一对下基板和上基板，电极和热电材料。 一对下基板和上基板布置成彼此面对。 电极形成在下基板的上表面和上基板的下表面上。 热电材料设置在电极之间。

    Semiconductor memory device with internal voltage generators for testing a memory array and peripheral circuits
    3.
    发明授权
    Semiconductor memory device with internal voltage generators for testing a memory array and peripheral circuits 有权
    具有用于测试存储器阵列和外围电路的内部电压发生器的半导体存储器件

    公开(公告)号：US06958947B2

    公开(公告)日：2005-10-25

    申请号：US10359075

    申请日：2003-02-06

    申请人： Chul-Sung Park ,  Hyang-Ja Yang ,  Seung-Min Lee ,  Yong-Hwan Noh

    发明人： Chul-Sung Park ,  Hyang-Ja Yang ,  Seung-Min Lee ,  Yong-Hwan Noh

    IPC分类号： G11C5/14 ,  G11C29/12 ,  G11C29/50

    CPC分类号： G11C29/12005 ,  G11C5/147 ,  G11C11/41 ,  G11C29/12 ,  G11C29/50 ,  G11C2207/2254

    摘要： A semiconductor memory device which includes an internal voltage generator circuit for adjusting an external power supply voltage and generating first and second internal power supply voltages. The first internal power supply voltage is supplied to a memory cell array via a first power supply line, and the second internal power supply voltage is supplied to a peripheral circuit via a second power supply line. A control circuit controls the internal voltage generator circuit so that the levels of the first and second internal power supply voltages vary depending on a mode of operation.

    摘要翻译： 一种半导体存储器件，包括用于调节外部电源电压并产生第一和第二内部电源电压的内部电压发生器电路。 第一内部电源电压经由第一电源线提供给存储单元阵列，并且第二内部电源电压经由第二电源线提供给外围电路。 控制电路控制内部电压发生器电路，使得第一和第二内部电源电压的电平根据操作模式而变化。

    Non-volatile memory device having a bit line contact pad and method for manufacturing the same
    4.
    发明授权
    Non-volatile memory device having a bit line contact pad and method for manufacturing the same 有权
    具有位线接触焊盘的非易失性存储器件及其制造方法

    公开(公告)号：US06744096B2

    公开(公告)日：2004-06-01

    申请号：US10453943

    申请日：2003-06-04

    申请人： Seung-Min Lee ,  Byung-Hong Chung

    发明人： Seung-Min Lee ,  Byung-Hong Chung

    IPC分类号： H01L29788

    CPC分类号： H01L21/76895 ,  H01L27/115 ,  H01L27/11521

    摘要： A non-volatile memory device and a method for manufacturing the same are disclosed. A non-volatile memory device comprises a semiconductor substrate having active areas which extend in a first direction and are repeatedly arranged in a second direction orthogonal to the first direction, a plurality of word lines formed on the semiconductor substrate which extending in the second direction while being repeatedly arranged in the first direction, string select lines adjacent to a first word line and extending in the second direction, ground select lines adjacent to a last word line and extending in the second direction, a first insulating interlayer formed on the resultant structure and comprising a first opening exposing the active area between the ground select lines and a second opening exposing the active area between the string select lines, a bit line contact pad formed in the second opening. A sidewall of the contact pad comprises a negative slope in the first direction and a positive slope in the second direction. A hard mask layer pattern, having the same pattern size as the active area, is formed on the contact pad and the first insulating interlayer. A second insulating interlayer is formed on the hard mask layer pattern and the first insulating interlayer. The second insulating interlayer has a bit line contact hole on the contact pad and thus the process margin is sufficiently achieved.

    摘要翻译： 公开了一种非易失性存储器件及其制造方法。 一种非易失性存储器件包括：半导体衬底，其具有沿第一方向延伸并且沿与第一方向正交的第二方向重复布置的有源区;多个字线，形成在半导体衬底上，沿第二方向延伸，同时 沿着第一方向重复地布置，与第一字线相邻并且在第二方向上延伸的串选择线，与最后字线相邻并在第二方向上延伸的接地选择线，在所得结构上形成的第一绝缘夹层， 包括暴露所述接地选择线之间的有源区域的第一开口和暴露所述串选择线之间的有源区域的第二开口，形成在所述第二开口中的位线接触焊盘。 接触垫的侧壁包括在第一方向上的负斜率和在第二方向上的正斜率。 在接触焊盘和第一绝缘中间层上形成具有与有源区相同的图案尺寸的硬掩模层图案。 在硬掩模层图案和第一绝缘中间层上形成第二绝缘中间层。 第二绝缘中间层在接触焊盘上具有位线接触孔，因此充分实现了工艺余量。

    Network correction security system and method
    8.
    再颁专利
    Network correction security system and method 有权
    网络校正安全系统及方法

    公开(公告)号：USRE45381E1

    公开(公告)日：2015-02-17

    申请号：US12954373

    申请日：2010-11-24

    申请人： Seung-Min Lee ,  Taek-Yong Nam ,  Sung-Won Sohn ,  Ye Seok Cho

    发明人： Seung-Min Lee ,  Taek-Yong Nam ,  Sung-Won Sohn ,  Chee-Hang Park

    IPC分类号： G06F9/00

    CPC分类号： H04L63/1458

    摘要： A network correction security system. The network correction security system connected between a network node and a security-related external system, detects attacks on the network node, corrects weak parts of the performance of the network node, collects information for improving the security performance of the network node from a security-related external system, analyzes the information, monitors principal resources of the network node to detect a fault, and removes the fault according to a measure corresponding to a grade of the fault. The network correction security system carries out a recovery process when the fault has not been corrected, and recovers the functions of the network node according to a recovery mechanism when the fault has not been removed after the recovery process.

    摘要翻译： 网络校正安全系统。 连接在网络节点和安全相关的外部系统之间的网络校正安全系统，检测对网络节点的攻击，纠正网络节点性能的弱点，从安全性中收集提高网络节点安全性能的信息 相关的外部系统，分析信息，监控网络节点的主要资源以检测故障，并根据与故障等级对应的措施消除故障。 网络校正安全系统在故障未得到纠正的情况下执行恢复过程，并且在恢复过程中还没有删除故障时，根据恢复机制恢复网络节点的功能。

    MIXER CIRCUIT
    9.
    发明申请
    MIXER CIRCUIT 审中-公开
    混频器电路

    公开(公告)号：US20110063013A1

    公开(公告)日：2011-03-17

    申请号：US12868003

    申请日：2010-08-25

    申请人： Young-Jin Kim ,  Il-Ho Na ,  Chun-Sik Jeong ,  Seong-Young Son ,  Seung-Min Lee ,  Myung-Woon Hwang

    发明人： Young-Jin Kim ,  Il-Ho Na ,  Chun-Sik Jeong ,  Seong-Young Son ,  Seung-Min Lee ,  Myung-Woon Hwang

    IPC分类号： G06G7/12

    CPC分类号： G06G7/16

    摘要： The present invention discloses a mixer circuit for mixing two input signals by source-coupled MOS transistors and outputting a mixed result. A duty cycle controlling MOS transistor is connected to a source of each source-coupled MOS transistor in series. A duty cycle controlling pulse is applied to a gate of the duty cycle controlling MOS transistor. The duty cycle controlling pulse has a phase shift of −90 degrees with respect to a controlling pulse applied to the gate of the source-coupled MOS transistor connected with the duty cycle controlling MOS transistor in series. An AND-combination of the duty cycles of the two controlling pulses applied to the gates of the two MOS transistors connected in series can be controlled at 25%. Comparing to the conventional mixer circuit having a switch control duty cycle of 50%, the present invention achieves the effects of increasing the gain and reducing the noise figure.

    摘要翻译： 本发明公开了一种用于通过源极耦合MOS晶体管混合两个输入信号并输出​​混合结果的混频器电路。 占空比控制MOS晶体管串联连接到每个源极耦合MOS晶体管的源极。 占空比控制脉冲施加到占空比控制MOS晶体管的栅极。 占空比控制脉冲相对于与占空比控制MOS晶体管串联连接的源极耦合MOS晶体管的栅极的控制脉冲具有-90度的相移。 施加到串联连接的两个MOS晶体管的栅极的两个控制脉冲的占空比的AND组合可以控制在25％。 与具有50％的开关控制占空比的常规混频器电路相比，本发明实现了增加增益和降低噪声系数的效果。

    CAPACITOR FOR SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    10.
    发明申请
    CAPACITOR FOR SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 审中-公开
    用于半导体器件的电容器及其制造方法

    公开(公告)号：US20090127655A1

    公开(公告)日：2009-05-21

    申请号：US12267566

    申请日：2008-11-08

    申请人： Seung-Min Lee

    发明人： Seung-Min Lee

    IPC分类号： H01L29/92 ,  H01L21/02

    CPC分类号： H01L28/40

    摘要： A capacitor for the semiconductor device may include a bottom electrode formed over a semiconductor substrate, a dielectric film pattern formed over the bottom electrode, an insulating member formed over a peripheral portion of the top surface of the dielectric film pattern, and a top electrode formed over the insulating member and dielectric film pattern. Capacitor properties are improved and capacitor values are maintained as constant by reducing a parasitic capacitance generated from edges of a capacitor electrode. Therefore, embodiments make it possible to improve semiconductor device properties and yields.

    摘要翻译： 用于半导体器件的电容器可以包括在半导体衬底上形成的底部电极，形成在底部电极上的电介质膜图案，形成在电介质膜图案的顶表面的周边部分上的绝缘构件和形成的顶部电极 超过绝缘构件和电介质膜图案。 改善了电容器性能，并且通过减小从电容器电极的边缘产生的寄生电容来将电容器值保持为恒定。 因此，实施例使得可以提高半导体器件性能和产量。