公开(公告)号：US08035779B2

公开(公告)日：2011-10-11

申请号：US12421115

申请日：2009-04-09

申请人： Seung-Soo Baek ,  Seong-Young Lee ,  Dong-Gyu Kim ,  Jang-Soo Kim

发明人： Seung-Soo Baek ,  Seong-Young Lee ,  Dong-Gyu Kim ,  Jang-Soo Kim

IPC分类号： G02F1/1333

CPC分类号： G02F1/1345 ,  G02F1/136209

摘要： A thin film transistor (“TFT”) array panel includes; a substrate including a display and peripheral area, a display area signal line and a display area TFT disposed in the display area, the display area TFT connected to the display area signal line, a plurality of peripheral area signal lines, a light blocking member disposed on the display area signal line, the display area TFT, and the peripheral area signal lines, a transparent connector connecting one of peripheral area signal lines and another one of the peripheral area signal lines through a contact hole passing through the light blocking member, a pixel electrode connected to the display area TFT, a spacer disposed on a layer above the light blocking member, and a light blocking assistance member composed of the same material as the spacer on the transparent connector, the light blocking assistance member covering at least the contact hole.

摘要翻译： 薄膜晶体管（“TFT”）阵列面板包括： 包括显示器和外围区域的基板，显示区域信号线和设置在显示区域中的显示区域TFT，连接到显示区域信号线的显示区域TFT，多个外围区域信号线， 显示区域信号线，显示区域TFT和外围区域信号线，通过穿过遮光构件的接触孔连接外围区域信号线和外围区域信号线中的一个的透明连接器， 连接到显示区域TFT的像素电极，设置在遮光构件上方的层的隔离物和由与透明连接器上的间隔物相同的材料构成的遮光辅助构件，遮光辅助构件至少覆盖接触部 孔。

公开(公告)号：US08648985B2

公开(公告)日：2014-02-11

申请号：US12612620

申请日：2009-11-04

申请人： Yong-Hwan Kim ,  Jang-Soo Kim ,  Hong-Suk Yoo ,  Seung-Soo Baek ,  Hwa-Yeul Oh ,  Jae-Ho Choi ,  Jong-In Kim ,  Sang-Hee Jang

发明人： Yong-Hwan Kim ,  Jang-Soo Kim ,  Hong-Suk Yoo ,  Seung-Soo Baek ,  Hwa-Yeul Oh ,  Jae-Ho Choi ,  Jong-In Kim ,  Sang-Hee Jang

IPC分类号： G02F1/1343 ,  G02F1/1368

CPC分类号： G02F1/136209

摘要： The present invention relates to a liquid crystal display. The liquid crystal display has a lower panel including a first pixel area having a first pixel electrode and a first light leakage preventing member, a final pixel area having a second pixel electrode and a second light leakage preventing member, and middle pixel areas disposed between the first pixel area and the final pixel area, each of the middle pixel areas including a first middle pixel electrode and a second middle pixel electrode. Accordingly, light leakage may be effectively prevented at the first pixel area and the final pixel area that are disposed on the edge.

摘要翻译： 本发明涉及一种液晶显示器。 液晶显示器具有包括具有第一像素电极和第一防漏光部件的第一像素区域，具有第二像素电极和第二防漏光部件的最终像素区域的下面板，以及设置在第二像素区域之间的中间像素区域 第一像素区域和最终像素区域，每个中间像素区域包括第一中间像素电极和第二中间像素电极。 因此，可以有效地防止在设置在边缘上的第一像素区域和最终像素区域处的光泄漏。

公开(公告)号：US20100245698A1

公开(公告)日：2010-09-30

申请号：US12612620

申请日：2009-11-04

申请人： Yong-Hwan Kim ,  Jang-Soo Kim ,  Hong-Suk Yoo ,  Seung-Soo Baek ,  Hwa-Yeul Oh ,  Jae-Ho Choi ,  Jong-In Kim ,  Sang-Hee Jang

发明人： Yong-Hwan Kim ,  Jang-Soo Kim ,  Hong-Suk Yoo ,  Seung-Soo Baek ,  Hwa-Yeul Oh ,  Jae-Ho Choi ,  Jong-In Kim ,  Sang-Hee Jang

IPC分类号： G02F1/136 ,  G02F1/1333

CPC分类号： G02F1/136209

摘要： The present invention relates to a liquid crystal display. The liquid crystal display has a lower panel including a first pixel area having a first pixel electrode and a first light leakage preventing member, a final pixel area having a second pixel electrode and a second light leakage preventing member, and middle pixel areas disposed between the first pixel area and the final pixel area, each of the middle pixel areas including a first middle pixel electrode and a second middle pixel electrode. Accordingly, light leakage may be effectively prevented at the first pixel area and the final pixel area that are disposed on the edge.

摘要翻译： 本发明涉及一种液晶显示器。 液晶显示器具有包括具有第一像素电极和第一防漏光部件的第一像素区域，具有第二像素电极和第二防漏光部件的最终像素区域的下面板，以及设置在第二像素区域之间的中间像素区域 第一像素区域和最终像素区域，每个中间像素区域包括第一中间像素电极和第二中间像素电极。 因此，可以有效地防止在设置在边缘上的第一像素区域和最终像素区域处的光泄漏。

公开(公告)号：US08598581B2

公开(公告)日：2013-12-03

申请号：US12434907

申请日：2009-05-04

申请人： Jang-Soo Kim ,  Jae-Hyoung Youn ,  Sang-Soo Kim ,  Dong-Gyu Kim

发明人： Jang-Soo Kim ,  Jae-Hyoung Youn ,  Sang-Soo Kim ,  Dong-Gyu Kim

IPC分类号： H01L33/00

CPC分类号： H01L29/78633 ,  H01L27/124 ,  H01L27/1248

摘要： A method for manufacturing a thin film transistor array panel includes; forming a gate line including a gate electrode and a height increasing member on a substrate, forming a gate insulating layer on the gate line and the height increasing member, forming a semiconductor, a data line including a source electrode, and a drain electrode facing the source electrode and overlapping at least a portion of the height increasing member on the gate insulating layer, forming a first insulating layer on the gate insulating layer, a data line and the drain electrode, forming a light-blocking member on a portion of the first insulating layer corresponding to the gate line and the data line, forming a color filter in an area bound by the light-blocking member, forming a second insulating layer on the light-blocking member and the color filter, and patterning the second insulating layer, the light-blocking member or the color filter, and the first insulating layer to form a contact hole exposing a portion of the drain electrode aligned with the height increasing member.

摘要翻译： 薄膜晶体管阵列板的制造方法包括： 在基板上形成包括栅电极和高度增加部件的栅极线，在栅极线和高度增加部件上形成栅绝缘层，形成半导体，包括源电极和漏电极的数据线， 并且在所述栅极绝缘层上与所述高度增加部件的至少一部分重叠，在所述栅极绝缘层上形成第一绝缘层，在所述栅极绝缘层上形成第一绝缘层，在所述栅极绝缘层上形成阻挡部件，在所述第一 对应于栅极线和数据线的绝缘层，在由阻光构件限定的区域中形成滤色器，在遮光构件和滤色器上形成第二绝缘层，并对第二绝缘层进行构图， 遮光构件或滤色器，以及第一绝缘层，以形成暴露与高度增加构件对准的漏电极的一部分的接触孔。

公开(公告)号：US20100012941A1

公开(公告)日：2010-01-21

申请号：US12570505

申请日：2009-09-30

申请人： Dong-Gyu Kim ,  Hyang-Shik Kong ,  Jang-Soo Kim

发明人： Dong-Gyu Kim ,  Hyang-Shik Kong ,  Jang-Soo Kim

IPC分类号： H01L27/12 ,  H01L21/77

CPC分类号： G02F1/136213 ,  G02F1/1337 ,  G02F1/133784 ,  G02F1/134336 ,  G02F1/136227 ,  G02F2201/123

摘要： A TFT array panel includes an insulating substrate, a gate line and a storage electrode line formed thereon. The gate line and the storage electrode line are covered with a gate insulating layer, and a semiconductor island is formed on the gate insulating layer. A pair of ohmic contacts are formed on the semiconductor island, and a data line and a drain electrode are formed thereon. The data line and the drain electrode are covered with a passivation layer having a contact hole exposing the drain electrode. A pixel electrode is formed on the passivation layer and connected to the drain electrode through the contact hole. The TFT array panel is covered with an alignment layer rubbed approximately in a direction from the upper left corner to the lower right corner of the TFT array panel or the pixel electrodes. The pixel electrode has approximately a rectangular shape and overlaps the gate line and the data line. The pixel electrode has an expansion located near the upper left corner of the pixel electrode to increase the width of the corresponding overlapping area between the pixel electrode and the gate line and/or the data line.

摘要翻译： TFT阵列面板包括绝缘基板，栅极线和形成在其上的存储电极线。 栅极线和存储电极线被栅极绝缘层覆盖，并且在栅极绝缘层上形成半导体岛。 在半导体岛上形成一对欧姆接触，在其上形成数据线和漏电极。 数据线和漏电极被具有暴露漏电极的接触孔的钝化层覆盖。 像素电极形成在钝化层上，并通过接触孔与漏电极连接。 TFT阵列面板被大致沿着从TFT阵列板的左上角到右下角或像素电极的方向摩擦的取向膜覆盖。 像素电极具有大致矩形形状并且与栅极线和数据线重叠。 像素电极具有位于像素电极的左上角附近的扩展部，以增加像素电极与栅极线和/或数据线之间的对应重叠区域的宽度。

公开(公告)号：US07408605B2

公开(公告)日：2008-08-05

申请号：US10790244

申请日：2004-03-02

申请人： Jin-Oh Kwag ,  Jang-Soo Kim ,  Kyung-Eun Lee ,  Dong-Gyu Kim

发明人： Jin-Oh Kwag ,  Jang-Soo Kim ,  Kyung-Eun Lee ,  Dong-Gyu Kim

IPC分类号： G02F1/1343 ,  G02F1/1337

CPC分类号： G02F1/134336 ,  G02F1/133707 ,  G02F1/1393

摘要： A pixel electrode is located in a pixel area defined by the intersections of the two adjacent gate lines and the two adjacent data lines, and has two linear openings extending in the transverse direction, which divide the pixel electrodes into three rectangular portions arranged in the longitudinal direction. The portions are connected in turn, and each portion of the pixel electrode has an X-shaped projection formed by the X-shaped member thereunder, and portions of the gate insulating film and the passivation film on the member. Since the gate insulating film and the passivation film are also located on the gate lines and the data lines, and the layered structure on the wires acts as peripheral projections of the pixel electrode. Each area enclosed by the projections, the openings and the peripheral projections is in a shape of equilateral trapezoid. The areas may be defined as the areas where the pixel electrode is in direct contact with the substrate. That is, each area has a planar shape of triangle, of which corner at the center of X-shape is chamfered. This structure causes a splay arrangement or a bend arrangement of the liquid crystal molecules in each domain, which is defined as a portion of the liquid crystal layer over each divided area, to be reinforced to improve the response time.

摘要翻译： 像素电极位于由两个相邻的栅极线和两个相邻的数据线的交点限定的像素区域中，并且具有在横向方向上延伸的两个线性开口，其将像素电极分成纵向排列的三个矩形部分 方向。 这些部分依次连接，并且像素电极的每个部分具有由其下方的X形构件形成的X形突起，并且部件上的栅极绝缘膜和钝化膜的部分。 由于栅绝缘膜和钝化膜也位于栅极线和数据线上，并且导线上的分层结构用作像素电极的周边突起。 由凸起包围的每个区域，开口和周边突起都是等边梯形的形状。 这些区域可以被定义为像素电极与衬底直接接触的区域。 也就是说，每个区域都具有三角形的平面形状，其中X形中心的角被倒角。 该结构使每个区域中的液晶分子的喷射布置或弯曲布置被限定为每个划分区域上的液晶层的一部分，以增强响应时间。

公开(公告)号：US20080030638A1

公开(公告)日：2008-02-07

申请号：US11873767

申请日：2007-10-17

申请人： Dong-Gyu Kim ,  Hyang-Shik Kong ,  Jang-Soo Kim

发明人： Dong-Gyu Kim ,  Hyang-Shik Kong ,  Jang-Soo Kim

IPC分类号： G02F1/1343

CPC分类号： G02F1/136213 ,  G02F1/1337 ,  G02F1/133784 ,  G02F1/134336 ,  G02F1/136227 ,  G02F2201/123

摘要： A TFT array panel includes an insulating substrate, a gate line and a storage electrode line formed thereon. The gate line and the storage electrode line are covered with a gate insulating layer, and a semiconductor island is formed on the gate insulating layer. A pair of ohmic contacts are formed on the semiconductor island, and a data line and a drain electrode are formed thereon. The data line and the drain electrode are covered with a passivation layer having a contact hole exposing the drain electrode. A pixel electrode is formed on the passivation layer and connected to the drain electrode through the contact hole. The TFT array panel is covered with an alignment layer rubbed approximately in a direction from the upper left corner to the lower right corner of the TFT array panel or the pixel electrodes. The pixel electrode has approximately a rectangular shape and overlaps the gate line and the data line. The pixel electrode has an expansion located near the upper left corner of the pixel electrode to increase the width of the corresponding overlapping area between the pixel electrode and the gate line and/or the data line.

摘要翻译： TFT阵列面板包括绝缘基板，栅极线和形成在其上的存储电极线。 栅极线和存储电极线被栅极绝缘层覆盖，并且在栅极绝缘层上形成半导体岛。 在半导体岛上形成一对欧姆接触，在其上形成数据线和漏电极。 数据线和漏电极被具有暴露漏电极的接触孔的钝化层覆盖。 像素电极形成在钝化层上，并通过接触孔与漏电极连接。 TFT阵列面板被大致沿着从TFT阵列板的左上角到右下角或像素电极的方向摩擦的取向膜覆盖。 像素电极具有大致矩形形状并且与栅极线和数据线重叠。 像素电极具有位于像素电极的左上角附近的扩展部，以增加像素电极与栅极线和/或数据线之间的对应重叠区域的宽度。

公开(公告)号：US06524876B1

公开(公告)日：2003-02-25

申请号：US09545891

申请日：2000-04-07

申请人： Bum-Ki Baek ,  Mun-Pyo Hong ,  Jang-Soo Kim ,  Sung-Wook Huh ,  Jong-Soo Yoon ,  Dong-Gyu Kim

发明人： Bum-Ki Baek ,  Mun-Pyo Hong ,  Jang-Soo Kim ,  Sung-Wook Huh ,  Jong-Soo Yoon ,  Dong-Gyu Kim

IPC分类号： H01L2100

CPC分类号： G02F1/13458 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/136236 ,  G02F2001/136272 ,  G02F2001/13629 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66765 ,  Y10S438/949

摘要： A conductive layer, including a lower layer made of refractory metal such as chromium, molybdenum, and molybdenum alloy and an upper layer made of aluminum or aluminum alloy, is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode on a substrate. At this time, the upper layer of the gate pad is removed using a photoresist pattern having different thicknesses depending on position as etch mask. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially formed. A conductive material is deposited and patterned to form a data wire including a data line, a source electrode, a drain electrode, and a data pad. Next, a passivation layer is deposited and patterned to form contact holes respectively exposing the drain electrode, the gate pad, and the data pad. At this time, the contact hole on the gate pad only exposes the lower layer of the gate pad, and the gate insulating layer and the passivation layer completely cover the upper layer of the gate pad. Next, indium tin oxide is deposited and patterned to form a pixel electrode, a redundant gate pad, and a redundant data pad respectively connected to the pixel electrode, the gate pad, and the data pad.

摘要翻译： 包括由诸如铬，钼和钼合金的难熔金属制成的下层和由铝或铝合金制成的上层的导电层被沉积和图案化以形成包括栅极线，栅极焊盘， 以及在基板上的栅电极。 此时，根据作为蚀刻掩模的位置，使用具有不同厚度的光致抗蚀剂图案去除栅极焊盘的上层。 依次形成栅极绝缘层，半导体层和欧姆接触层。 导电材料被沉积并图案化以形成包括数据线，源电极，漏电极和数据焊盘的数据线。 接下来，沉积并图案化钝化层以形成分别暴露漏电极，栅极焊盘和数据焊盘的接触孔。 此时，栅极焊盘上的接触孔仅暴露栅极焊盘的下层，栅极绝缘层和钝化层完全覆盖栅极焊盘的上层。 接下来，沉积和图案化氧化铟锡以形成分别连接到像素电极，栅极焊盘和数据焊盘的像素电极，冗余栅极焊盘和冗余数据焊盘。

公开(公告)号：US07289171B2

公开(公告)日：2007-10-30

申请号：US11551450

申请日：2006-10-20

申请人： Dong-Gyu Kim ,  Hyang-Shik Kong ,  Jang-Soo Kim

发明人： Dong-Gyu Kim ,  Hyang-Shik Kong ,  Jang-Soo Kim

IPC分类号： G02F1/136 ,  G02F1/1343

CPC分类号： G02F1/136213 ,  G02F1/1337 ,  G02F1/133784 ,  G02F1/134336 ,  G02F1/136227 ,  G02F2201/123

摘要： A TFT array panel includes an insulating substrate, a gate line and a storage electrode line formed thereon. The gate line and the storage electrode line are covered with a gate insulating layer, and a semiconductor island is formed on the gate insulating layer. A pair of ohmic contacts are formed on the semiconductor island, and a data line and a drain electrode are formed thereon. The data line and the drain electrode are covered with a passivation layer having a contact hole exposing the drain electrode. A pixel electrode is formed on the passivation layer and connected to the drain electrode through the contact hole. The TFT array panel is covered with an alignment layer rubbed approximately in a direction from the upper left corner to the lower right corner of the TFT array panel or the pixel electrodes. The pixel electrode has approximately a rectangular shape and overlaps the gate line and the data line. The pixel electrode has an expansion located near the upper left corner of the pixel electrode to increase the width of the corresponding overlapping area between the pixel electrode and the gate line and/or the data line.

摘要翻译： TFT阵列面板包括绝缘基板，栅极线和形成在其上的存储电极线。 栅极线和存储电极线被栅极绝缘层覆盖，并且在栅极绝缘层上形成半导体岛。 在半导体岛上形成一对欧姆接触，在其上形成数据线和漏电极。 数据线和漏电极被具有暴露漏电极的接触孔的钝化层覆盖。 像素电极形成在钝化层上，并通过接触孔与漏电极连接。 TFT阵列面板被大致沿着从TFT阵列板的左上角到右下角或像素电极的方向摩擦的取向膜覆盖。 像素电极具有大致矩形形状并且与栅极线和数据线重叠。 像素电极具有位于像素电极的左上角附近的扩展部，以增加像素电极与栅极线和/或数据线之间的对应重叠区域的宽度。

公开(公告)号：US20050170592A1

公开(公告)日：2005-08-04

申请号：US11080612

申请日：2005-03-16

申请人： Bum-Ki Baek ,  Mun-Pyo Hong ,  Jang-Soo Kim ,  Sung-Wook Huh ,  Jong-Soo Yoon ,  Dong-Gyu Kim

发明人： Bum-Ki Baek ,  Mun-Pyo Hong ,  Jang-Soo Kim ,  Sung-Wook Huh ,  Jong-Soo Yoon ,  Dong-Gyu Kim

IPC分类号： G02F1/1362 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L31/0376

CPC分类号： G02F1/13458 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/136236 ,  G02F2001/136272 ,  G02F2001/13629 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66765 ,  Y10S438/949

摘要： A conductive layer, including a lower layer made of refractory metal such as chromium, molybdenum, and molybdenum alloy and an upper layer made of aluminum or aluminum alloy, is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode on a substrate. At this time, the upper layer of the gate pad is removed using a photoresist pattern having different thicknesses depending on position as etch mask. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially formed. A conductive material is deposited and patterned to form a data wire including a data line, a source electrode, a drain electrode, and a data pad. Next, a passivation layer is deposited and patterned to form contact holes respectively exposing the drain electrode, the gate pad, and the data pad. At this time, the contact hole on the gate pad only exposes the lower layer of the gate pad, and the gate insulating layer and the passivation layer completely cover the upper layer of the gate pad. Next, indium tin oxide is deposited and patterned to form a pixel electrode, a redundant gate pad, and a redundant data pad respectively connected to the pixel electrode, the gate pad, and the data pad.

摘要翻译： 包括由诸如铬，钼和钼合金的难熔金属制成的下层和由铝或铝合金制成的上层的导电层被沉积和图案化以形成包括栅极线，栅极焊盘， 以及在基板上的栅电极。 此时，根据作为蚀刻掩模的位置，使用具有不同厚度的光致抗蚀剂图案去除栅极焊盘的上层。 依次形成栅极绝缘层，半导体层和欧姆接触层。 导电材料被沉积并图案化以形成包括数据线，源电极，漏电极和数据焊盘的数据线。 接下来，沉积并图案化钝化层以形成分别暴露漏电极，栅极焊盘和数据焊盘的接触孔。 此时，栅极焊盘上的接触孔仅暴露栅极焊盘的下层，栅极绝缘层和钝化层完全覆盖栅极焊盘的上层。 接下来，沉积和图案化氧化铟锡以形成分别连接到像素电极，栅极焊盘和数据焊盘的像素电极，冗余栅极焊盘和冗余数据焊盘。