公开(公告)号：US06181605B2

公开(公告)日：2001-01-30

申请号：US09414750

申请日：1999-10-06

申请人： Shane C. Hollmer ,  Joseph G. Pawletko ,  Michael S. C. Chung

发明人： Shane C. Hollmer ,  Joseph G. Pawletko ,  Michael S. C. Chung

IPC分类号： G11C1606

CPC分类号： G11C16/3445 ,  G11C16/0483 ,  G11C16/3436 ,  G11C16/3459

摘要： A technique to determine whether multiple memory cells are programmed or erased. After a program or erase operation, respective program or erase verify operations are performed. A logical gate is coupled to measure the state of each memory cell. When all memory cells selected to be programmed or erased are programmed or erased then the output of the logical gate indicates successful program or erase verify. Thus, by using a single logical gate coupled to measure the states of multiple memory cells, only the output of the logical gate need be measured to determine successful program or erase verification of multiple memory cells.

摘要翻译： 确定多个存储器单元是否被编程或擦除的技术。 在编程或擦除操作之后，执行相应的编程或擦除验证操作。 耦合逻辑门来测量每个存储单元的状态。 当所有被选择被编程或擦除的存储单元被编程或擦除时，逻辑门的输出指示成功的程序或擦除验证。 因此，通过使用耦合以测量多个存储器单元的状态的单个逻辑门，仅需要测量逻辑门的输出以确定多个存储单元的成功编程或擦除验证。

公开(公告)号：US5995417A

公开(公告)日：1999-11-30

申请号：US175646

申请日：1998-10-20

申请人： Pau-Ling Chen ,  Michael S. C. Chung ,  Shane C. Hollmer ,  Vincent Leung ,  Binh Quang Le ,  Masaru Yano

发明人： Pau-Ling Chen ,  Michael S. C. Chung ,  Shane C. Hollmer ,  Vincent Leung ,  Binh Quang Le ,  Masaru Yano

IPC分类号： G11C16/02 ,  G11C16/16 ,  G11C16/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/3445 ,  G11C16/16 ,  G11C16/344

摘要： A non-volatile memory device includes a plurality of MOS transistors 34 and 36 connected to respective word lines 16 and 18 to allow individual pages of memory stored in the memory cells 8a, 10a and 8b, 10b on the respective word lines 16 and 18 to be erased and erase verified. A method of erasing a page of memory cells includes the steps of applying an erase voltage to one of the MOS transistors 16 and 18 to erase the page of memory cells along the respective word line, and applying an initial erase-inhibit floating voltage to other MOS transistors which are connected to the word lines unselected for page erase. In an erase verify mode, an erase verify voltage is applied to the word line which was selected for page erase in the erase mode, and an erase verify unselect voltage is applied to the word lines which was not selected for page erase.

摘要翻译： 非易失性存储器件包括连接到各个字线16和18的多个MOS晶体管34和36，以允许存储在相应字线16和18上的存储器单元8a，10a和8b，10b中的存储器的各页 被擦除和擦除验证。 擦除一页存储单元的方法包括以下步骤：将擦除电压施加到MOS晶体管16和18中的一个以擦除沿着相应字线的存储单元的页面，并将初始擦除禁止浮动电压施加到其他 连接到未选择用于页面擦除的字线的MOS晶体管。 在擦除验证模式下，擦除验证电压被施加到在擦除模式下被选择用于页擦除的字线，并且擦除验证未选择电压被施加到未被选择用于页擦除的字线。

公开(公告)号：US5978267A

公开(公告)日：1999-11-02

申请号：US175647

申请日：1998-10-20

申请人： Pau-Ling Chen ,  Michael Van Buskirk ,  Shane C. Hollmer ,  Michael S. C. Chung ,  Binh Quang Le ,  Vincent Leung ,  Shoichi Kawamura ,  Masaru Yano

发明人： Pau-Ling Chen ,  Michael Van Buskirk ,  Shane C. Hollmer ,  Michael S. C. Chung ,  Binh Quang Le ,  Vincent Leung ,  Shoichi Kawamura ,  Masaru Yano

IPC分类号： G11C16/02 ,  G11C7/12 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C7/12

摘要： In the programming of a non-volatile memory device, such as a NAND flash memory device 100, a positive bias voltage V.sub.bias is applied to a bit line 44 to set a respective memory gate 44a in a programmed state. In a further embodiment, the positive bias voltage V.sub.bias is obtained by dividing the select drain gate voltage V.sub.cc using two resistors 56 and 58 connected in series.

摘要翻译： 在非易失性存储器件（例如NAND闪速存储器件100）的编程中，将正偏置电压Vbias施加到位线44以将相应的存储器栅极44a设置为编程状态。 在另一实施例中，通过使用串联连接的两个电阻器56和58分压选择漏极栅极电压Vcc来获得正偏置电压Vbias。

公开(公告)号：US06370061B1

公开(公告)日：2002-04-09

申请号：US09884583

申请日：2001-06-19

申请人： Santosh K. Yachareni ,  Kazuhiro Kurihara ,  Binh Q. Le ,  Michael S. C. Chung

发明人： Santosh K. Yachareni ,  Kazuhiro Kurihara ,  Binh Q. Le ,  Michael S. C. Chung

IPC分类号： G11C1634

CPC分类号： G11C16/3459 ,  G11C16/04 ,  G11C16/3454 ,  G11C16/349 ,  G11C29/50 ,  G11C29/50004

摘要： The present invention relates to flash memory systems and methods to determine the threshold voltage of core cells. In one exemplary system, there is provided a method of characterizing the high end of the threshold voltage distribution of an array of programmed cells. In accordance with the invention, an exemplary system and method are presented to apply a varying characterization signal operably through a high breakdown voltage periphery donut transistor and wordline drive transistors, which are driven into saturation by a boosted gate voltage which is higher than the applied varying characterization signal, in a manner which provides for the accurate determination of the VT of the core cells, through the comparison of the conduction in a reference cell to that of the conduction in a core cell produced by a varying characterization signal applied to the core cell gate.

摘要翻译： 本发明涉及闪存系统和确定核心单元的阈值电压的方法。 在一个示例性系统中，提供了表征编程单元阵列的阈值电压分布的高端的方法。 根据本发明，提出了一种示例性的系统和方法，以通过高耐压周边环形晶体管和字线驱动晶体管可操作地应用变化的特征信号，该晶体管和字线驱动晶体管通过高于施加的变化的升压栅极电压而被驱动为饱和 表征信号，以提供核心单元的VT的精确确定的方式，通过比较参考单元中的导通与通过施加到核心单元的变化表征信号产生的核心单元中的导通的比较 门。

公开(公告)号：US07002381B1

公开(公告)日：2006-02-21

申请号：US10015033

申请日：2001-12-11

申请人： Michael S. C. Chung

发明人： Michael S. C. Chung

IPC分类号： H03K4/06

CPC分类号： H02M3/07 ,  G11C16/12 ,  G11C16/30 ,  H02M1/36 ,  H03K4/023

摘要： A switched capacitor controller accurately controls the rise time of an on-chip generated high voltage. An on-chip charge pump is used to generate a high voltage (VPP) from an external power supply voltage (VCC). This high voltage signal (VPP) can be used to program Flash memory cells. A capacitor of a switched capacitor circuit is selectively switched between ground and a given node voltage. This generates a stair-stepped ramp function. The period of the steps is controlled according to a clock signal. This clock signal may be altered to produce the desired period. The voltage increases of the steps is regulated by a reference voltage multiplied by a ratio between two capacitor values. Thereby, the rise-time of the ramp function is accurately controlled as a function of the frequency of the clock signal and the ratio of the two capacitor values.

摘要翻译： 开关电容器控制器可精确控制片内产生的高电压的上升时间。 使用片上电荷泵从外部电源电压（VCC）产生高电压（VPP）。 该高电压信号（VPP）可用于对闪存单元进行编程。 开关电容器电路的电容器选择性地在接地和给定的节点电压之间切换。 这产生阶梯式斜坡功能。 根据时钟信号控制步长的周期。 可以改变该时钟信号以产生期望的周期。 步长的电压增加由参考电压乘以两个电容值之间的比值来调节。 因此，斜坡函数的上升时间被精确地控制为时钟信号的频率和两个电容器值的比率的函数。

公开(公告)号：US06510082B1

公开(公告)日：2003-01-21

申请号：US09999869

申请日：2001-10-23

申请人： Binh Q. Le ,  Pau-Ling Chen ,  Michael A. Van Buskirk ,  Santosh K. Yachareni ,  Michael S. C. Chung ,  Kazuhiro Kurihara ,  Shane Hollmer

发明人： Binh Q. Le ,  Pau-Ling Chen ,  Michael A. Van Buskirk ,  Santosh K. Yachareni ,  Michael S. C. Chung ,  Kazuhiro Kurihara ,  Shane Hollmer

IPC分类号： G11C1604

CPC分类号： G11C16/0491 ,  G11C16/28

摘要： A system is disclosed for producing an indication of the logical state of a flash memory cell for virtual ground flash memory operations. The system comprises a bit line charge and hold circuit which is operable to apply a read sense voltage (e.g., about 1.2 volts) to a bit line associated with the drain terminal of a cell of the flash array adjacent to the cell which is sensed, wherein the applied drain terminal voltage is substantially the same as the cell sense voltage (e.g., about 1.2 volts) applied to the drain terminal bit line of the selected memory cell to be sensed. The system further includes a selective bit line decode circuit which is operable to select the bit lines of a memory cell to be sensed and the bit line of an adjacent cell, and a core cell sensing circuit which is operable to sense a core cell sense current at a bit line associated with a drain terminal of the selected memory cell to be sensed during memory read operations, and produce an indication of the flash memory cell logical state, which is substantially independent of charge sharing leakage current to an adjacent cell.

摘要翻译： 公开了一种用于产生用于虚拟接地闪速存储器操作的闪存单元的逻辑状态的指示的系统。 该系统包括位线充电和保持电路，其可操作以将读取感测电压（例如，约1.2伏特）施加到与所感测的电池相邻的闪光阵列的单元的漏极端子相关联的位线， 其中所施加的漏极端子电压基本上与施加到要被感测的所选择的存储器单元的漏极端子位线的单元检测电压（例如，约1.2伏特）相同。 该系统还包括选择性位线解码电路，其可操作以选择要感测的存储器单元的位线和相邻单元的位线;以及核心单元感测电路，其可操作以感测核心单元感测电流 在与存储器读取操作期间被感测的所选择的存储器单元的漏极端子相关联的位线处，并产生闪存单元逻辑状态的指示，其基本上与相邻单元的电荷共享泄漏电流无关。

公开(公告)号：US5959477A

公开(公告)日：1999-09-28

申请号：US88828

申请日：1998-06-02

申请人： Michael S. C. Chung

发明人： Michael S. C. Chung

IPC分类号： H03K17/22 ,  H03L7/00

CPC分类号： H03K17/223

摘要： A precision power-on reset circuit which is highly insensitive to temperature and process variations includes a self-biased proportional-to-absolute-temperature (PTAT) current generator 4, a base-emitter (V.sub.BE) voltage detector 6, and a bipolar complementary metal oxide semiconductor (BiCMOS) inverter 8, which generates a power-on reset pulse for resetting an application circuit when a power supply voltage is turned on. The power-on reset circuit may further include a complementary metal oxide semiconductor (CMOS) buffer 10 coupled to the BiCMOS inverter 8 to isolate the application circuit from currents in the power-on reset circuit.

摘要翻译： 对温度和工艺变化高度不敏感的精密上电复位电路包括自偏压比例绝对温度（PTAT）电流发生器4，基极 - 发射极（VBE）电压检测器6和双极互补 金属氧化物半导体（BiCMOS）反相器8，其在电源电压接通时产生用于复位施加电路的上电复位脉冲。 上电复位电路还可以包括耦合到BiCMOS反相器8的互补金属氧化物半导体（CMOS）缓冲器10，以将施加电路与上电复位电路中的电流隔离。

公开(公告)号：US6137324A

公开(公告)日：2000-10-24

申请号：US345056

申请日：1999-06-30

申请人： Michael S. C. Chung

发明人： Michael S. C. Chung

IPC分类号： H03K17/22 ,  H03L7/00

CPC分类号： H03K17/223

摘要： The present invention is a power-on reset circuit that generates a precise power-on reset pulse with an upper threshold voltage that is highly insensitive to variations in temperature and integrated circuit fabrication processes. The power-on reset circuit of the present invention includes a self-biased current generator capable of receiving a supply voltage and generating a first current, which is proportional to an absolute temperature, in response to receiving the supply voltage. The power-on reset circuit of the present invention also includes a base-emitter voltage detector that is coupled to the self-biased current generator such that a second current flowing though the base-emitter voltage detector is substantially equal to the first current generated by the self-biased current generator. Furthermore, the power-on reset circuit of the present invention includes a (BiCMOS) inverter that is coupled to the base-emitter voltage detector such that the BiCMOS inverter generates the power-on reset pulse as the supply voltage is turned on. With such a power-on reset circuit of the present invention, the upper threshold voltage of the power-on reset pulse may be optimized to be independent of the absolute temperature and to be insensitive to variations in the power supply voltage and in integrated circuit fabrication process parameters. In addition, the upper threshold voltage of the power-on reset pulse of the present invention is independent of a voltage across a drain and source of any MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with the power-on reset circuit topology of the present invention.

摘要翻译： 本发明是一种上电复位电路，其产生具有对温度变化和集成电路制造工艺高度不敏感的较高阈值电压的精确上电复位脉冲。 本发明的上电复位电路包括响应于接收电源电压而能够接收电源电压并产生与绝对温度成正比的第一电流的自偏置电流发生器。 本发明的上电复位电路还包括耦合到自偏置电流发生器的基极 - 发射极电压检测器，使得流经基极 - 发射极电压检测器的第二电流基本上等于由 自偏置电流发生器。 此外，本发明的上电复位电路包括（BiCMOS）反相器，其耦合到基极 - 发射极电压检测器，使得BiCMOS反相器在电源电压接通时产生上电复位脉冲。 利用本发明的这种上电复位电路，上电复位脉冲的上阈值电压可以被优化为独立于绝对温度，并且对电源电压的变化和集成电路制造不敏感 工艺参数。 此外，本发明的上电复位脉冲的上限阈值电压与具有本发明的上电复位电路拓扑的任何MOSFET（金属氧化物半导体场效应晶体管）的漏极和源极之间的电压无关 发明。